Twilight Princess
Decompilation of The Legend of Zelda: Twilight Princess
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cp_reg.h
Go to the documentation of this file.
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#ifndef __FDL_CP_REG_H__
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#define __FDL_CP_REG_H__
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#include <
revolution/private/GXFDLShortcut.h
>
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#define FDL_ASSERT(c)
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#define CP_CMD_NOP 0x00
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#define CP_CMD_QUADS 0x10
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#define CP_CMD_QUAD_STRIP 0x11
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#define CP_CMD_TRIANGLES 0x12
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#define CP_CMD_TRIANGLE_STRIP 0x13
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#define CP_CMD_TRIANGLE_FAN 0x14
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#define CP_CMD_LINES 0x15
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#define CP_CMD_LINE_STRIP 0x16
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#define CP_CMD_POINTS 0x17
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#define CP_CMD_LOADREGS 0x01
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#define CP_CMD_XF_LOADREGS 0x02
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#define CP_CMD_XF_IDXLDREG_A 0x04
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#define CP_CMD_XF_IDXLDREG_B 0x05
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#define CP_CMD_XF_IDXLDREG_C 0x06
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#define CP_CMD_XF_IDXLDREG_D 0x07
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#define CP_CMD_CALL_OBJECT 0x08
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#define CP_CMD_VCACHE_INVALIDATE 0x09
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#define CP_CMD_SU_BYPCMD0 0x0c
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#define CP_CMD_SU_BYPCMD1 0x0d
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#define CP_COUNTER0L 0x20
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#define CP_COUNTER0H 0x21
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#define CP_COUNTER1L 0x22
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#define CP_COUNTER1H 0x23
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#define CP_COUNTER2L 0x24
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#define CP_COUNTER2H 0x25
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#define CP_COUNTER3L 0x26
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#define CP_COUNTER3H 0x27
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#define CP_VC_CHKCNTL 0x28
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#define CP_VC_CHKCNTH 0x29
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#define CP_OPCODE_INDEX_SIZE 3
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#define CP_OPCODE_INDEX_SHIFT 0
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#define CP_OPCODE_INDEX_MASK 0x00000007
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#define CP_OPCODE_GET_INDEX(cp_opcode) \
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((((unsigned long)(cp_opcode)) & CP_OPCODE_INDEX_MASK) >> CP_OPCODE_INDEX_SHIFT)
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#define CP_OPCODE_SET_INDEX(cp_opcode, index) { \
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FDL_ASSERT(!((index) & ~((1 << CP_OPCODE_INDEX_SIZE)-1))); \
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cp_opcode = (((unsigned long)(cp_opcode)) & ~CP_OPCODE_INDEX_MASK) | (((unsigned long)(index)) << CP_OPCODE_INDEX_SHIFT);\
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}
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#define CP_OPCODE_CMD_SIZE 5
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#define CP_OPCODE_CMD_SHIFT 3
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#define CP_OPCODE_CMD_MASK 0x000000f8
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#define CP_OPCODE_GET_CMD(cp_opcode) \
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((((unsigned long)(cp_opcode)) & CP_OPCODE_CMD_MASK) >> CP_OPCODE_CMD_SHIFT)
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#define CP_OPCODE_SET_CMD(cp_opcode, cmd) { \
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FDL_ASSERT(!((cmd) & ~((1 << CP_OPCODE_CMD_SIZE)-1))); \
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cp_opcode = (((unsigned long)(cp_opcode)) & ~CP_OPCODE_CMD_MASK) | (((unsigned long)(cmd)) << CP_OPCODE_CMD_SHIFT);\
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}
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#define CP_OPCODE_TOTAL_SIZE 8
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#define CP_OPCODE(index, cmd) \
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((((unsigned long)(index)) << CP_OPCODE_INDEX_SHIFT) | \
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(((unsigned long)(cmd)) << CP_OPCODE_CMD_SHIFT))
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#define CP_VC_STAT_RESET 0x00
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#define CP_STAT_ENABLE 0x01
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#define CP_STAT_SEL 0x02
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#define CP_MATINDEX_A 0x03
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#define CP_MATINDEX_B 0x04
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#define CP_VCD_LO 0x05
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#define CP_VCD_HI 0x06
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#define CP_VAT_A 0x07
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#define CP_VAT_B 0x08
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#define CP_VAT_C 0x09
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#define CP_ARRAY_BASE 0x0a
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#define CP_ARRAY_STRIDE 0x0b
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#define CP_STREAM_REG_INDEX_SIZE 4
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#define CP_STREAM_REG_INDEX_SHIFT 0
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#define CP_STREAM_REG_INDEX_MASK 0x0000000f
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#define CP_STREAM_REG_GET_INDEX(cp_stream_reg) \
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((((unsigned long)(cp_stream_reg)) & CP_STREAM_REG_INDEX_MASK) >> CP_STREAM_REG_INDEX_SHIFT)
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#define CP_STREAM_REG_SET_INDEX(cp_stream_reg, index) { \
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FDL_ASSERT(!((index) & ~((1 << CP_STREAM_REG_INDEX_SIZE)-1))); \
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cp_stream_reg = (((unsigned long)(cp_stream_reg)) & ~CP_STREAM_REG_INDEX_MASK) | (((unsigned long)(index)) << CP_STREAM_REG_INDEX_SHIFT);\
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}
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#define CP_STREAM_REG_ADDR_SIZE 4
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#define CP_STREAM_REG_ADDR_SHIFT 4
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#define CP_STREAM_REG_ADDR_MASK 0x000000f0
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#define CP_STREAM_REG_GET_ADDR(cp_stream_reg) \
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((((unsigned long)(cp_stream_reg)) & CP_STREAM_REG_ADDR_MASK) >> CP_STREAM_REG_ADDR_SHIFT)
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#define CP_STREAM_REG_SET_ADDR(cp_stream_reg, addr) { \
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FDL_ASSERT(!((addr) & ~((1 << CP_STREAM_REG_ADDR_SIZE)-1))); \
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cp_stream_reg = (((unsigned long)(cp_stream_reg)) & ~CP_STREAM_REG_ADDR_MASK) | (((unsigned long)(addr)) << CP_STREAM_REG_ADDR_SHIFT);\
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}
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#define CP_STREAM_REG_TOTAL_SIZE 8
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#define CP_STREAM_REG(index, addr) \
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((((unsigned long)(index)) << CP_STREAM_REG_INDEX_SHIFT) | \
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(((unsigned long)(addr)) << CP_STREAM_REG_ADDR_SHIFT))
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#define CP_STATUS 0x00
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#define CP_ENABLE 0x01
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#define CP_CLR 0x02
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#define CP_MEMPERF_SEL 0x03
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#define CP_STM_LOW 0x05
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#define CP_FIFO_BASEL 0x10
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#define CP_FIFO_BASEH 0x11
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#define CP_FIFO_TOPL 0x12
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#define CP_FIFO_TOPH 0x13
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#define CP_FIFO_HICNTL 0x14
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#define CP_FIFO_HICNTH 0x15
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#define CP_FIFO_LOCNTL 0x16
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#define CP_FIFO_LOCNTH 0x17
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#define CP_FIFO_COUNTL 0x18
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#define CP_FIFO_COUNTH 0x19
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#define CP_FIFO_WPTRL 0x1a
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#define CP_FIFO_WPTRH 0x1b
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#define CP_FIFO_RPTRL 0x1c
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#define CP_FIFO_RPTRH 0x1d
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#define CP_FIFO_BRKL 0x1e
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#define CP_FIFO_BRKH 0x1f
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#define CP_COUNTER0L 0x20
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#define CP_COUNTER0H 0x21
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#define CP_COUNTER1L 0x22
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#define CP_COUNTER1H 0x23
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#define CP_COUNTER2L 0x24
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#define CP_COUNTER2H 0x25
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#define CP_COUNTER3L 0x26
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#define CP_COUNTER3H 0x27
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#define CP_VC_CHKCNTL 0x28
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#define CP_VC_CHKCNTH 0x29
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#define CP_VC_MISSL 0x2a
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#define CP_VC_MISSH 0x2b
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#define CP_VC_STALLL 0x2c
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#define CP_VC_STALLH 0x2d
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#define CP_FRCLK_CNTL 0x2e
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#define CP_FRCLK_CNTH 0x2f
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#define CP_XF_ADDR 0x30
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#define CP_XF_DATAL 0x31
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#define CP_XF_DATAH 0x32
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#define CP_NUM_REGS 0x33
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/*
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* cp_reg_status struct
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*/
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#define CP_REG_STATUS_OVFL_SIZE 1
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#define CP_REG_STATUS_OVFL_SHIFT 0
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#define CP_REG_STATUS_OVFL_MASK 0x00000001
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#define CP_REG_STATUS_GET_OVFL(cp_reg_status) \
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((((unsigned long)(cp_reg_status)) & CP_REG_STATUS_OVFL_MASK) >> CP_REG_STATUS_OVFL_SHIFT)
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#define CP_REG_STATUS_SET_OVFL(cp_reg_status, ovfl) { \
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FDL_ASSERT(!((ovfl) & ~((1 << CP_REG_STATUS_OVFL_SIZE)-1))); \
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cp_reg_status = (((unsigned long)(cp_reg_status)) & ~CP_REG_STATUS_OVFL_MASK) | (((unsigned long)(ovfl)) << CP_REG_STATUS_OVFL_SHIFT);\
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}
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#define CP_REG_STATUS_UNFL_SIZE 1
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#define CP_REG_STATUS_UNFL_SHIFT 1
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#define CP_REG_STATUS_UNFL_MASK 0x00000002
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#define CP_REG_STATUS_GET_UNFL(cp_reg_status) \
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((((unsigned long)(cp_reg_status)) & CP_REG_STATUS_UNFL_MASK) >> CP_REG_STATUS_UNFL_SHIFT)
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#define CP_REG_STATUS_SET_UNFL(cp_reg_status, unfl) { \
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FDL_ASSERT(!((unfl) & ~((1 << CP_REG_STATUS_UNFL_SIZE)-1))); \
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cp_reg_status = (((unsigned long)(cp_reg_status)) & ~CP_REG_STATUS_UNFL_MASK) | (((unsigned long)(unfl)) << CP_REG_STATUS_UNFL_SHIFT);\
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}
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#define CP_REG_STATUS_FIFO_RDIDLE_SIZE 1
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#define CP_REG_STATUS_FIFO_RDIDLE_SHIFT 2
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#define CP_REG_STATUS_FIFO_RDIDLE_MASK 0x00000004
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#define CP_REG_STATUS_GET_FIFO_RDIDLE(cp_reg_status) \
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((((unsigned long)(cp_reg_status)) & CP_REG_STATUS_FIFO_RDIDLE_MASK) >> CP_REG_STATUS_FIFO_RDIDLE_SHIFT)
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#define CP_REG_STATUS_SET_FIFO_RDIDLE(cp_reg_status, fifo_rdidle) { \
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FDL_ASSERT(!((fifo_rdidle) & ~((1 << CP_REG_STATUS_FIFO_RDIDLE_SIZE)-1))); \
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cp_reg_status = (((unsigned long)(cp_reg_status)) & ~CP_REG_STATUS_FIFO_RDIDLE_MASK) | (((unsigned long)(fifo_rdidle)) << CP_REG_STATUS_FIFO_RDIDLE_SHIFT);\
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}
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#define CP_REG_STATUS_CPIDLE_SIZE 1
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#define CP_REG_STATUS_CPIDLE_SHIFT 3
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#define CP_REG_STATUS_CPIDLE_MASK 0x00000008
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#define CP_REG_STATUS_GET_CPIDLE(cp_reg_status) \
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((((unsigned long)(cp_reg_status)) & CP_REG_STATUS_CPIDLE_MASK) >> CP_REG_STATUS_CPIDLE_SHIFT)
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#define CP_REG_STATUS_SET_CPIDLE(cp_reg_status, cpidle) { \
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FDL_ASSERT(!((cpidle) & ~((1 << CP_REG_STATUS_CPIDLE_SIZE)-1))); \
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cp_reg_status = (((unsigned long)(cp_reg_status)) & ~CP_REG_STATUS_CPIDLE_MASK) | (((unsigned long)(cpidle)) << CP_REG_STATUS_CPIDLE_SHIFT);\
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}
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#define CP_REG_STATUS_FIFOBRK_SIZE 1
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#define CP_REG_STATUS_FIFOBRK_SHIFT 4
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#define CP_REG_STATUS_FIFOBRK_MASK 0x00000010
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#define CP_REG_STATUS_GET_FIFOBRK(cp_reg_status) \
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((((unsigned long)(cp_reg_status)) & CP_REG_STATUS_FIFOBRK_MASK) >> CP_REG_STATUS_FIFOBRK_SHIFT)
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#define CP_REG_STATUS_SET_FIFOBRK(cp_reg_status, fifobrk) { \
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FDL_ASSERT(!((fifobrk) & ~((1 << CP_REG_STATUS_FIFOBRK_SIZE)-1))); \
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cp_reg_status = (((unsigned long)(cp_reg_status)) & ~CP_REG_STATUS_FIFOBRK_MASK) | (((unsigned long)(fifobrk)) << CP_REG_STATUS_FIFOBRK_SHIFT);\
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}
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#define CP_REG_STATUS_TOTAL_SIZE 5
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#define CP_REG_STATUS(ovfl, unfl, fifo_rdidle, cpidle, fifobrk) \
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((((unsigned long)(ovfl)) << CP_REG_STATUS_OVFL_SHIFT) | \
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(((unsigned long)(unfl)) << CP_REG_STATUS_UNFL_SHIFT) | \
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(((unsigned long)(fifo_rdidle)) << CP_REG_STATUS_FIFO_RDIDLE_SHIFT) | \
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(((unsigned long)(cpidle)) << CP_REG_STATUS_CPIDLE_SHIFT) | \
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(((unsigned long)(fifobrk)) << CP_REG_STATUS_FIFOBRK_SHIFT))
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/*
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* cp_reg_enable struct
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*/
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#define CP_REG_ENABLE_FIFORD_SIZE 1
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#define CP_REG_ENABLE_FIFORD_SHIFT 0
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#define CP_REG_ENABLE_FIFORD_MASK 0x00000001
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#define CP_REG_ENABLE_GET_FIFORD(cp_reg_enable) \
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((((unsigned long)(cp_reg_enable)) & CP_REG_ENABLE_FIFORD_MASK) >> CP_REG_ENABLE_FIFORD_SHIFT)
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#define CP_REG_ENABLE_SET_FIFORD(cp_reg_enable, fiford) { \
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FDL_ASSERT(!((fiford) & ~((1 << CP_REG_ENABLE_FIFORD_SIZE)-1))); \
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cp_reg_enable = (((unsigned long)(cp_reg_enable)) & ~CP_REG_ENABLE_FIFORD_MASK) | (((unsigned long)(fiford)) << CP_REG_ENABLE_FIFORD_SHIFT);\
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}
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#define CP_REG_ENABLE_FIFOBRK_SIZE 1
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#define CP_REG_ENABLE_FIFOBRK_SHIFT 1
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#define CP_REG_ENABLE_FIFOBRK_MASK 0x00000002
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#define CP_REG_ENABLE_GET_FIFOBRK(cp_reg_enable) \
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((((unsigned long)(cp_reg_enable)) & CP_REG_ENABLE_FIFOBRK_MASK) >> CP_REG_ENABLE_FIFOBRK_SHIFT)
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#define CP_REG_ENABLE_SET_FIFOBRK(cp_reg_enable, fifobrk) { \
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FDL_ASSERT(!((fifobrk) & ~((1 << CP_REG_ENABLE_FIFOBRK_SIZE)-1))); \
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cp_reg_enable = (((unsigned long)(cp_reg_enable)) & ~CP_REG_ENABLE_FIFOBRK_MASK) | (((unsigned long)(fifobrk)) << CP_REG_ENABLE_FIFOBRK_SHIFT);\
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}
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#define CP_REG_ENABLE_OVFLINT_SIZE 1
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#define CP_REG_ENABLE_OVFLINT_SHIFT 2
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#define CP_REG_ENABLE_OVFLINT_MASK 0x00000004
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#define CP_REG_ENABLE_GET_OVFLINT(cp_reg_enable) \
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((((unsigned long)(cp_reg_enable)) & CP_REG_ENABLE_OVFLINT_MASK) >> CP_REG_ENABLE_OVFLINT_SHIFT)
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#define CP_REG_ENABLE_SET_OVFLINT(cp_reg_enable, ovflint) { \
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FDL_ASSERT(!((ovflint) & ~((1 << CP_REG_ENABLE_OVFLINT_SIZE)-1))); \
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cp_reg_enable = (((unsigned long)(cp_reg_enable)) & ~CP_REG_ENABLE_OVFLINT_MASK) | (((unsigned long)(ovflint)) << CP_REG_ENABLE_OVFLINT_SHIFT);\
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}
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#define CP_REG_ENABLE_UNFLINT_SIZE 1
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#define CP_REG_ENABLE_UNFLINT_SHIFT 3
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#define CP_REG_ENABLE_UNFLINT_MASK 0x00000008
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#define CP_REG_ENABLE_GET_UNFLINT(cp_reg_enable) \
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((((unsigned long)(cp_reg_enable)) & CP_REG_ENABLE_UNFLINT_MASK) >> CP_REG_ENABLE_UNFLINT_SHIFT)
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#define CP_REG_ENABLE_SET_UNFLINT(cp_reg_enable, unflint) { \
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FDL_ASSERT(!((unflint) & ~((1 << CP_REG_ENABLE_UNFLINT_SIZE)-1))); \
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cp_reg_enable = (((unsigned long)(cp_reg_enable)) & ~CP_REG_ENABLE_UNFLINT_MASK) | (((unsigned long)(unflint)) << CP_REG_ENABLE_UNFLINT_SHIFT);\
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}
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#define CP_REG_ENABLE_WRPTRINC_SIZE 1
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#define CP_REG_ENABLE_WRPTRINC_SHIFT 4
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#define CP_REG_ENABLE_WRPTRINC_MASK 0x00000010
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#define CP_REG_ENABLE_GET_WRPTRINC(cp_reg_enable) \
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((((unsigned long)(cp_reg_enable)) & CP_REG_ENABLE_WRPTRINC_MASK) >> CP_REG_ENABLE_WRPTRINC_SHIFT)
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#define CP_REG_ENABLE_SET_WRPTRINC(cp_reg_enable, wrptrinc) { \
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FDL_ASSERT(!((wrptrinc) & ~((1 << CP_REG_ENABLE_WRPTRINC_SIZE)-1))); \
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cp_reg_enable = (((unsigned long)(cp_reg_enable)) & ~CP_REG_ENABLE_WRPTRINC_MASK) | (((unsigned long)(wrptrinc)) << CP_REG_ENABLE_WRPTRINC_SHIFT);\
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}
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#define CP_REG_ENABLE_FIFOBRKINT_SIZE 1
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#define CP_REG_ENABLE_FIFOBRKINT_SHIFT 5
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#define CP_REG_ENABLE_FIFOBRKINT_MASK 0x00000020
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#define CP_REG_ENABLE_GET_FIFOBRKINT(cp_reg_enable) \
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((((unsigned long)(cp_reg_enable)) & CP_REG_ENABLE_FIFOBRKINT_MASK) >> CP_REG_ENABLE_FIFOBRKINT_SHIFT)
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#define CP_REG_ENABLE_SET_FIFOBRKINT(cp_reg_enable, fifobrkint) { \
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FDL_ASSERT(!((fifobrkint) & ~((1 << CP_REG_ENABLE_FIFOBRKINT_SIZE)-1))); \
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cp_reg_enable = (((unsigned long)(cp_reg_enable)) & ~CP_REG_ENABLE_FIFOBRKINT_MASK) | (((unsigned long)(fifobrkint)) << CP_REG_ENABLE_FIFOBRKINT_SHIFT);\
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}
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#define CP_REG_ENABLE_TOTAL_SIZE 6
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#define CP_REG_ENABLE(fiford, fifobrk, ovflint, unflint, wrptrinc, fifobrkint) \
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((((unsigned long)(fiford)) << CP_REG_ENABLE_FIFORD_SHIFT) | \
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(((unsigned long)(fifobrk)) << CP_REG_ENABLE_FIFOBRK_SHIFT) | \
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(((unsigned long)(ovflint)) << CP_REG_ENABLE_OVFLINT_SHIFT) | \
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(((unsigned long)(unflint)) << CP_REG_ENABLE_UNFLINT_SHIFT) | \
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(((unsigned long)(wrptrinc)) << CP_REG_ENABLE_WRPTRINC_SHIFT) | \
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(((unsigned long)(fifobrkint)) << CP_REG_ENABLE_FIFOBRKINT_SHIFT))
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/*
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* cp_reg_clr struct
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*/
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#define CP_REG_CLR_OVFLINT_SIZE 1
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#define CP_REG_CLR_OVFLINT_SHIFT 0
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#define CP_REG_CLR_OVFLINT_MASK 0x00000001
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#define CP_REG_CLR_GET_OVFLINT(cp_reg_clr) \
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((((unsigned long)(cp_reg_clr)) & CP_REG_CLR_OVFLINT_MASK) >> CP_REG_CLR_OVFLINT_SHIFT)
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#define CP_REG_CLR_SET_OVFLINT(cp_reg_clr, ovflint) { \
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FDL_ASSERT(!((ovflint) & ~((1 << CP_REG_CLR_OVFLINT_SIZE)-1))); \
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cp_reg_clr = (((unsigned long)(cp_reg_clr)) & ~CP_REG_CLR_OVFLINT_MASK) | (((unsigned long)(ovflint)) << CP_REG_CLR_OVFLINT_SHIFT);\
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}
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#define CP_REG_CLR_UNFLINT_SIZE 1
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#define CP_REG_CLR_UNFLINT_SHIFT 1
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#define CP_REG_CLR_UNFLINT_MASK 0x00000002
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#define CP_REG_CLR_GET_UNFLINT(cp_reg_clr) \
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((((unsigned long)(cp_reg_clr)) & CP_REG_CLR_UNFLINT_MASK) >> CP_REG_CLR_UNFLINT_SHIFT)
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#define CP_REG_CLR_SET_UNFLINT(cp_reg_clr, unflint) { \
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FDL_ASSERT(!((unflint) & ~((1 << CP_REG_CLR_UNFLINT_SIZE)-1))); \
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cp_reg_clr = (((unsigned long)(cp_reg_clr)) & ~CP_REG_CLR_UNFLINT_MASK) | (((unsigned long)(unflint)) << CP_REG_CLR_UNFLINT_SHIFT);\
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}
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#define CP_REG_CLR_PERFCNT_SIZE 1
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#define CP_REG_CLR_PERFCNT_SHIFT 2
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#define CP_REG_CLR_PERFCNT_MASK 0x00000004
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#define CP_REG_CLR_GET_PERFCNT(cp_reg_clr) \
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((((unsigned long)(cp_reg_clr)) & CP_REG_CLR_PERFCNT_MASK) >> CP_REG_CLR_PERFCNT_SHIFT)
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#define CP_REG_CLR_SET_PERFCNT(cp_reg_clr, perfcnt) { \
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FDL_ASSERT(!((perfcnt) & ~((1 << CP_REG_CLR_PERFCNT_SIZE)-1))); \
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cp_reg_clr = (((unsigned long)(cp_reg_clr)) & ~CP_REG_CLR_PERFCNT_MASK) | (((unsigned long)(perfcnt)) << CP_REG_CLR_PERFCNT_SHIFT);\
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}
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#define CP_REG_CLR_TOTAL_SIZE 3
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#define CP_REG_CLR(ovflint, unflint, perfcnt) \
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((((unsigned long)(ovflint)) << CP_REG_CLR_OVFLINT_SHIFT) | \
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(((unsigned long)(unflint)) << CP_REG_CLR_UNFLINT_SHIFT) | \
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(((unsigned long)(perfcnt)) << CP_REG_CLR_PERFCNT_SHIFT))
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/*
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* cp_reg_memperfsel struct
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*/
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#define CP_REG_MEMPERFSEL_PERFSEL_SIZE 3
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#define CP_REG_MEMPERFSEL_PERFSEL_SHIFT 0
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#define CP_REG_MEMPERFSEL_PERFSEL_MASK 0x00000007
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#define CP_REG_MEMPERFSEL_GET_PERFSEL(cp_reg_memperfsel) \
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((((unsigned long)(cp_reg_memperfsel)) & CP_REG_MEMPERFSEL_PERFSEL_MASK) >> CP_REG_MEMPERFSEL_PERFSEL_SHIFT)
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#define CP_REG_MEMPERFSEL_SET_PERFSEL(cp_reg_memperfsel, perfsel) { \
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FDL_ASSERT(!((perfsel) & ~((1 << CP_REG_MEMPERFSEL_PERFSEL_SIZE)-1))); \
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cp_reg_memperfsel = (((unsigned long)(cp_reg_memperfsel)) & ~CP_REG_MEMPERFSEL_PERFSEL_MASK) | (((unsigned long)(perfsel)) << CP_REG_MEMPERFSEL_PERFSEL_SHIFT);\
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}
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#define CP_REG_MEMPERFSEL_TOTAL_SIZE 3
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#define CP_REG_MEMPERFSEL(perfsel) \
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((((unsigned long)(perfsel)) << CP_REG_MEMPERFSEL_PERFSEL_SHIFT))
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/*
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* cp_reg_fifo_basel struct
316
*/
317
#define CP_REG_FIFO_BASEL_PAD0_SIZE 5
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#define CP_REG_FIFO_BASEL_PAD0_SHIFT 0
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#define CP_REG_FIFO_BASEL_PAD0_MASK 0x0000001f
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#define CP_REG_FIFO_BASEL_GET_PAD0(cp_reg_fifo_basel) \
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((((unsigned long)(cp_reg_fifo_basel)) & CP_REG_FIFO_BASEL_PAD0_MASK) >> CP_REG_FIFO_BASEL_PAD0_SHIFT)
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#define CP_REG_FIFO_BASEL_SET_PAD0(cp_reg_fifo_basel, pad0) { \
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FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_BASEL_PAD0_SIZE)-1))); \
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cp_reg_fifo_basel = (((unsigned long)(cp_reg_fifo_basel)) & ~CP_REG_FIFO_BASEL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_BASEL_PAD0_SHIFT);\
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}
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#define CP_REG_FIFO_BASEL_ADDR_SIZE 11
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#define CP_REG_FIFO_BASEL_ADDR_SHIFT 5
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#define CP_REG_FIFO_BASEL_ADDR_MASK 0x0000ffe0
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#define CP_REG_FIFO_BASEL_GET_ADDR(cp_reg_fifo_basel) \
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((((unsigned long)(cp_reg_fifo_basel)) & CP_REG_FIFO_BASEL_ADDR_MASK) >> CP_REG_FIFO_BASEL_ADDR_SHIFT)
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#define CP_REG_FIFO_BASEL_SET_ADDR(cp_reg_fifo_basel, addr) { \
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FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_BASEL_ADDR_SIZE)-1))); \
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cp_reg_fifo_basel = (((unsigned long)(cp_reg_fifo_basel)) & ~CP_REG_FIFO_BASEL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_BASEL_ADDR_SHIFT);\
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}
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#define CP_REG_FIFO_BASEL_TOTAL_SIZE 16
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#define CP_REG_FIFO_BASEL(addr) \
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((((unsigned long)(addr)) << CP_REG_FIFO_BASEL_ADDR_SHIFT))
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/*
340
* cp_reg_fifo_baseh struct
341
*/
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#define CP_REG_FIFO_BASEH_ADDR_SIZE 13
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#define CP_REG_FIFO_BASEH_ADDR_SHIFT 0
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#define CP_REG_FIFO_BASEH_ADDR_MASK 0x00001fff
345
#define CP_REG_FIFO_BASEH_GET_ADDR(cp_reg_fifo_baseh) \
346
((((unsigned long)(cp_reg_fifo_baseh)) & CP_REG_FIFO_BASEH_ADDR_MASK) >> CP_REG_FIFO_BASEH_ADDR_SHIFT)
347
#define CP_REG_FIFO_BASEH_SET_ADDR(cp_reg_fifo_baseh, addr) { \
348
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_BASEH_ADDR_SIZE)-1))); \
349
cp_reg_fifo_baseh = (((unsigned long)(cp_reg_fifo_baseh)) & ~CP_REG_FIFO_BASEH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_BASEH_ADDR_SHIFT);\
350
}
351
#define CP_REG_FIFO_BASEH_TOTAL_SIZE 13
352
#define CP_REG_FIFO_BASEH(addr) \
353
((((unsigned long)(addr)) << CP_REG_FIFO_BASEH_ADDR_SHIFT))
354
355
/*
356
* cp_reg_fifo_topl struct
357
*/
358
#define CP_REG_FIFO_TOPL_PAD0_SIZE 5
359
#define CP_REG_FIFO_TOPL_PAD0_SHIFT 0
360
#define CP_REG_FIFO_TOPL_PAD0_MASK 0x0000001f
361
#define CP_REG_FIFO_TOPL_GET_PAD0(cp_reg_fifo_topl) \
362
((((unsigned long)(cp_reg_fifo_topl)) & CP_REG_FIFO_TOPL_PAD0_MASK) >> CP_REG_FIFO_TOPL_PAD0_SHIFT)
363
#define CP_REG_FIFO_TOPL_SET_PAD0(cp_reg_fifo_topl, pad0) { \
364
FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_TOPL_PAD0_SIZE)-1))); \
365
cp_reg_fifo_topl = (((unsigned long)(cp_reg_fifo_topl)) & ~CP_REG_FIFO_TOPL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_TOPL_PAD0_SHIFT);\
366
}
367
#define CP_REG_FIFO_TOPL_ADDR_SIZE 11
368
#define CP_REG_FIFO_TOPL_ADDR_SHIFT 5
369
#define CP_REG_FIFO_TOPL_ADDR_MASK 0x0000ffe0
370
#define CP_REG_FIFO_TOPL_GET_ADDR(cp_reg_fifo_topl) \
371
((((unsigned long)(cp_reg_fifo_topl)) & CP_REG_FIFO_TOPL_ADDR_MASK) >> CP_REG_FIFO_TOPL_ADDR_SHIFT)
372
#define CP_REG_FIFO_TOPL_SET_ADDR(cp_reg_fifo_topl, addr) { \
373
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_TOPL_ADDR_SIZE)-1))); \
374
cp_reg_fifo_topl = (((unsigned long)(cp_reg_fifo_topl)) & ~CP_REG_FIFO_TOPL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_TOPL_ADDR_SHIFT);\
375
}
376
#define CP_REG_FIFO_TOPL_TOTAL_SIZE 16
377
#define CP_REG_FIFO_TOPL(addr) \
378
((((unsigned long)(addr)) << CP_REG_FIFO_TOPL_ADDR_SHIFT))
379
380
/*
381
* cp_reg_fifo_toph struct
382
*/
383
#define CP_REG_FIFO_TOPH_ADDR_SIZE 13
384
#define CP_REG_FIFO_TOPH_ADDR_SHIFT 0
385
#define CP_REG_FIFO_TOPH_ADDR_MASK 0x00001fff
386
#define CP_REG_FIFO_TOPH_GET_ADDR(cp_reg_fifo_toph) \
387
((((unsigned long)(cp_reg_fifo_toph)) & CP_REG_FIFO_TOPH_ADDR_MASK) >> CP_REG_FIFO_TOPH_ADDR_SHIFT)
388
#define CP_REG_FIFO_TOPH_SET_ADDR(cp_reg_fifo_toph, addr) { \
389
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_TOPH_ADDR_SIZE)-1))); \
390
cp_reg_fifo_toph = (((unsigned long)(cp_reg_fifo_toph)) & ~CP_REG_FIFO_TOPH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_TOPH_ADDR_SHIFT);\
391
}
392
#define CP_REG_FIFO_TOPH_TOTAL_SIZE 13
393
#define CP_REG_FIFO_TOPH(addr) \
394
((((unsigned long)(addr)) << CP_REG_FIFO_TOPH_ADDR_SHIFT))
395
396
/*
397
* cp_reg_fifo_hicntl struct
398
*/
399
#define CP_REG_FIFO_HICNTL_PAD0_SIZE 5
400
#define CP_REG_FIFO_HICNTL_PAD0_SHIFT 0
401
#define CP_REG_FIFO_HICNTL_PAD0_MASK 0x0000001f
402
#define CP_REG_FIFO_HICNTL_GET_PAD0(cp_reg_fifo_hicntl) \
403
((((unsigned long)(cp_reg_fifo_hicntl)) & CP_REG_FIFO_HICNTL_PAD0_MASK) >> CP_REG_FIFO_HICNTL_PAD0_SHIFT)
404
#define CP_REG_FIFO_HICNTL_SET_PAD0(cp_reg_fifo_hicntl, pad0) { \
405
FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_HICNTL_PAD0_SIZE)-1))); \
406
cp_reg_fifo_hicntl = (((unsigned long)(cp_reg_fifo_hicntl)) & ~CP_REG_FIFO_HICNTL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_HICNTL_PAD0_SHIFT);\
407
}
408
#define CP_REG_FIFO_HICNTL_ADDR_SIZE 11
409
#define CP_REG_FIFO_HICNTL_ADDR_SHIFT 5
410
#define CP_REG_FIFO_HICNTL_ADDR_MASK 0x0000ffe0
411
#define CP_REG_FIFO_HICNTL_GET_ADDR(cp_reg_fifo_hicntl) \
412
((((unsigned long)(cp_reg_fifo_hicntl)) & CP_REG_FIFO_HICNTL_ADDR_MASK) >> CP_REG_FIFO_HICNTL_ADDR_SHIFT)
413
#define CP_REG_FIFO_HICNTL_SET_ADDR(cp_reg_fifo_hicntl, addr) { \
414
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_HICNTL_ADDR_SIZE)-1))); \
415
cp_reg_fifo_hicntl = (((unsigned long)(cp_reg_fifo_hicntl)) & ~CP_REG_FIFO_HICNTL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_HICNTL_ADDR_SHIFT);\
416
}
417
#define CP_REG_FIFO_HICNTL_TOTAL_SIZE 16
418
#define CP_REG_FIFO_HICNTL(addr) \
419
((((unsigned long)(addr)) << CP_REG_FIFO_HICNTL_ADDR_SHIFT))
420
421
/*
422
* cp_reg_fifo_hicnth struct
423
*/
424
#define CP_REG_FIFO_HICNTH_ADDR_SIZE 13
425
#define CP_REG_FIFO_HICNTH_ADDR_SHIFT 0
426
#define CP_REG_FIFO_HICNTH_ADDR_MASK 0x00001fff
427
#define CP_REG_FIFO_HICNTH_GET_ADDR(cp_reg_fifo_hicnth) \
428
((((unsigned long)(cp_reg_fifo_hicnth)) & CP_REG_FIFO_HICNTH_ADDR_MASK) >> CP_REG_FIFO_HICNTH_ADDR_SHIFT)
429
#define CP_REG_FIFO_HICNTH_SET_ADDR(cp_reg_fifo_hicnth, addr) { \
430
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_HICNTH_ADDR_SIZE)-1))); \
431
cp_reg_fifo_hicnth = (((unsigned long)(cp_reg_fifo_hicnth)) & ~CP_REG_FIFO_HICNTH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_HICNTH_ADDR_SHIFT);\
432
}
433
#define CP_REG_FIFO_HICNTH_TOTAL_SIZE 13
434
#define CP_REG_FIFO_HICNTH(addr) \
435
((((unsigned long)(addr)) << CP_REG_FIFO_HICNTH_ADDR_SHIFT))
436
437
#define CP_REG_FIFO_LOCNTL_PAD0_SIZE 5
438
#define CP_REG_FIFO_LOCNTL_PAD0_SHIFT 0
439
#define CP_REG_FIFO_LOCNTL_PAD0_MASK 0x0000001f
440
#define CP_REG_FIFO_LOCNTL_GET_PAD0(cp_reg_fifo_locntl) \
441
((((unsigned long)(cp_reg_fifo_locntl)) & CP_REG_FIFO_LOCNTL_PAD0_MASK) >> CP_REG_FIFO_LOCNTL_PAD0_SHIFT)
442
#define CP_REG_FIFO_LOCNTL_SET_PAD0(cp_reg_fifo_locntl, pad0) { \
443
FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_LOCNTL_PAD0_SIZE)-1))); \
444
cp_reg_fifo_locntl = (((unsigned long)(cp_reg_fifo_locntl)) & ~CP_REG_FIFO_LOCNTL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_LOCNTL_PAD0_SHIFT);\
445
}
446
#define CP_REG_FIFO_LOCNTL_ADDR_SIZE 11
447
#define CP_REG_FIFO_LOCNTL_ADDR_SHIFT 5
448
#define CP_REG_FIFO_LOCNTL_ADDR_MASK 0x0000ffe0
449
#define CP_REG_FIFO_LOCNTL_GET_ADDR(cp_reg_fifo_locntl) \
450
((((unsigned long)(cp_reg_fifo_locntl)) & CP_REG_FIFO_LOCNTL_ADDR_MASK) >> CP_REG_FIFO_LOCNTL_ADDR_SHIFT)
451
#define CP_REG_FIFO_LOCNTL_SET_ADDR(cp_reg_fifo_locntl, addr) { \
452
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_LOCNTL_ADDR_SIZE)-1))); \
453
cp_reg_fifo_locntl = (((unsigned long)(cp_reg_fifo_locntl)) & ~CP_REG_FIFO_LOCNTL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_LOCNTL_ADDR_SHIFT);\
454
}
455
#define CP_REG_FIFO_LOCNTL_TOTAL_SIZE 16
456
#define CP_REG_FIFO_LOCNTL(addr) \
457
((((unsigned long)(addr)) << CP_REG_FIFO_LOCNTL_ADDR_SHIFT))
458
459
#define CP_REG_FIFO_LOCNTH_ADDR_SIZE 13
460
#define CP_REG_FIFO_LOCNTH_ADDR_SHIFT 0
461
#define CP_REG_FIFO_LOCNTH_ADDR_MASK 0x00001fff
462
#define CP_REG_FIFO_LOCNTH_GET_ADDR(cp_reg_fifo_locnth) \
463
((((unsigned long)(cp_reg_fifo_locnth)) & CP_REG_FIFO_LOCNTH_ADDR_MASK) >> CP_REG_FIFO_LOCNTH_ADDR_SHIFT)
464
#define CP_REG_FIFO_LOCNTH_SET_ADDR(cp_reg_fifo_locnth, addr) { \
465
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_LOCNTH_ADDR_SIZE)-1))); \
466
cp_reg_fifo_locnth = (((unsigned long)(cp_reg_fifo_locnth)) & ~CP_REG_FIFO_LOCNTH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_LOCNTH_ADDR_SHIFT);\
467
}
468
#define CP_REG_FIFO_LOCNTH_TOTAL_SIZE 13
469
#define CP_REG_FIFO_LOCNTH(addr) \
470
((((unsigned long)(addr)) << CP_REG_FIFO_LOCNTH_ADDR_SHIFT))
471
472
#define CP_REG_FIFO_COUNTL_PAD0_SIZE 5
473
#define CP_REG_FIFO_COUNTL_PAD0_SHIFT 0
474
#define CP_REG_FIFO_COUNTL_PAD0_MASK 0x0000001f
475
#define CP_REG_FIFO_COUNTL_GET_PAD0(cp_reg_fifo_countl) \
476
((((unsigned long)(cp_reg_fifo_countl)) & CP_REG_FIFO_COUNTL_PAD0_MASK) >> CP_REG_FIFO_COUNTL_PAD0_SHIFT)
477
#define CP_REG_FIFO_COUNTL_SET_PAD0(cp_reg_fifo_countl, pad0) { \
478
FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_COUNTL_PAD0_SIZE)-1))); \
479
cp_reg_fifo_countl = (((unsigned long)(cp_reg_fifo_countl)) & ~CP_REG_FIFO_COUNTL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_COUNTL_PAD0_SHIFT);\
480
}
481
#define CP_REG_FIFO_COUNTL_ADDR_SIZE 11
482
#define CP_REG_FIFO_COUNTL_ADDR_SHIFT 5
483
#define CP_REG_FIFO_COUNTL_ADDR_MASK 0x0000ffe0
484
#define CP_REG_FIFO_COUNTL_GET_ADDR(cp_reg_fifo_countl) \
485
((((unsigned long)(cp_reg_fifo_countl)) & CP_REG_FIFO_COUNTL_ADDR_MASK) >> CP_REG_FIFO_COUNTL_ADDR_SHIFT)
486
#define CP_REG_FIFO_COUNTL_SET_ADDR(cp_reg_fifo_countl, addr) { \
487
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_COUNTL_ADDR_SIZE)-1))); \
488
cp_reg_fifo_countl = (((unsigned long)(cp_reg_fifo_countl)) & ~CP_REG_FIFO_COUNTL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_COUNTL_ADDR_SHIFT);\
489
}
490
#define CP_REG_FIFO_COUNTL_TOTAL_SIZE 16
491
#define CP_REG_FIFO_COUNTL(addr) \
492
((((unsigned long)(addr)) << CP_REG_FIFO_COUNTL_ADDR_SHIFT))
493
494
#define CP_REG_FIFO_COUNTH_ADDR_SIZE 13
495
#define CP_REG_FIFO_COUNTH_ADDR_SHIFT 0
496
#define CP_REG_FIFO_COUNTH_ADDR_MASK 0x00001fff
497
#define CP_REG_FIFO_COUNTH_GET_ADDR(cp_reg_fifo_counth) \
498
((((unsigned long)(cp_reg_fifo_counth)) & CP_REG_FIFO_COUNTH_ADDR_MASK) >> CP_REG_FIFO_COUNTH_ADDR_SHIFT)
499
#define CP_REG_FIFO_COUNTH_SET_ADDR(cp_reg_fifo_counth, addr) { \
500
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_COUNTH_ADDR_SIZE)-1))); \
501
cp_reg_fifo_counth = (((unsigned long)(cp_reg_fifo_counth)) & ~CP_REG_FIFO_COUNTH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_COUNTH_ADDR_SHIFT);\
502
}
503
#define CP_REG_FIFO_COUNTH_TOTAL_SIZE 13
504
#define CP_REG_FIFO_COUNTH(addr) \
505
((((unsigned long)(addr)) << CP_REG_FIFO_COUNTH_ADDR_SHIFT))
506
507
#define CP_REG_FIFO_WPTRL_PAD0_SIZE 5
508
#define CP_REG_FIFO_WPTRL_PAD0_SHIFT 0
509
#define CP_REG_FIFO_WPTRL_PAD0_MASK 0x0000001f
510
#define CP_REG_FIFO_WPTRL_GET_PAD0(cp_reg_fifo_wptrl) \
511
((((unsigned long)(cp_reg_fifo_wptrl)) & CP_REG_FIFO_WPTRL_PAD0_MASK) >> CP_REG_FIFO_WPTRL_PAD0_SHIFT)
512
#define CP_REG_FIFO_WPTRL_SET_PAD0(cp_reg_fifo_wptrl, pad0) { \
513
FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_WPTRL_PAD0_SIZE)-1))); \
514
cp_reg_fifo_wptrl = (((unsigned long)(cp_reg_fifo_wptrl)) & ~CP_REG_FIFO_WPTRL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_WPTRL_PAD0_SHIFT);\
515
}
516
#define CP_REG_FIFO_WPTRL_ADDR_SIZE 11
517
#define CP_REG_FIFO_WPTRL_ADDR_SHIFT 5
518
#define CP_REG_FIFO_WPTRL_ADDR_MASK 0x0000ffe0
519
#define CP_REG_FIFO_WPTRL_GET_ADDR(cp_reg_fifo_wptrl) \
520
((((unsigned long)(cp_reg_fifo_wptrl)) & CP_REG_FIFO_WPTRL_ADDR_MASK) >> CP_REG_FIFO_WPTRL_ADDR_SHIFT)
521
#define CP_REG_FIFO_WPTRL_SET_ADDR(cp_reg_fifo_wptrl, addr) { \
522
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_WPTRL_ADDR_SIZE)-1))); \
523
cp_reg_fifo_wptrl = (((unsigned long)(cp_reg_fifo_wptrl)) & ~CP_REG_FIFO_WPTRL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_WPTRL_ADDR_SHIFT);\
524
}
525
#define CP_REG_FIFO_WPTRL_TOTAL_SIZE 16
526
#define CP_REG_FIFO_WPTRL(addr) \
527
((((unsigned long)(addr)) << CP_REG_FIFO_WPTRL_ADDR_SHIFT))
528
529
#define CP_REG_FIFO_WPTRH_ADDR_SIZE 13
530
#define CP_REG_FIFO_WPTRH_ADDR_SHIFT 0
531
#define CP_REG_FIFO_WPTRH_ADDR_MASK 0x00001fff
532
#define CP_REG_FIFO_WPTRH_GET_ADDR(cp_reg_fifo_wptrh) \
533
((((unsigned long)(cp_reg_fifo_wptrh)) & CP_REG_FIFO_WPTRH_ADDR_MASK) >> CP_REG_FIFO_WPTRH_ADDR_SHIFT)
534
#define CP_REG_FIFO_WPTRH_SET_ADDR(cp_reg_fifo_wptrh, addr) { \
535
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_WPTRH_ADDR_SIZE)-1))); \
536
cp_reg_fifo_wptrh = (((unsigned long)(cp_reg_fifo_wptrh)) & ~CP_REG_FIFO_WPTRH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_WPTRH_ADDR_SHIFT);\
537
}
538
#define CP_REG_FIFO_WPTRH_TOTAL_SIZE 13
539
#define CP_REG_FIFO_WPTRH(addr) \
540
((((unsigned long)(addr)) << CP_REG_FIFO_WPTRH_ADDR_SHIFT))
541
542
#define CP_REG_FIFO_RPTRL_PAD0_SIZE 5
543
#define CP_REG_FIFO_RPTRL_PAD0_SHIFT 0
544
#define CP_REG_FIFO_RPTRL_PAD0_MASK 0x0000001f
545
#define CP_REG_FIFO_RPTRL_GET_PAD0(cp_reg_fifo_rptrl) \
546
((((unsigned long)(cp_reg_fifo_rptrl)) & CP_REG_FIFO_RPTRL_PAD0_MASK) >> CP_REG_FIFO_RPTRL_PAD0_SHIFT)
547
#define CP_REG_FIFO_RPTRL_SET_PAD0(cp_reg_fifo_rptrl, pad0) { \
548
FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_RPTRL_PAD0_SIZE)-1))); \
549
cp_reg_fifo_rptrl = (((unsigned long)(cp_reg_fifo_rptrl)) & ~CP_REG_FIFO_RPTRL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_RPTRL_PAD0_SHIFT);\
550
}
551
#define CP_REG_FIFO_RPTRL_ADDR_SIZE 11
552
#define CP_REG_FIFO_RPTRL_ADDR_SHIFT 5
553
#define CP_REG_FIFO_RPTRL_ADDR_MASK 0x0000ffe0
554
#define CP_REG_FIFO_RPTRL_GET_ADDR(cp_reg_fifo_rptrl) \
555
((((unsigned long)(cp_reg_fifo_rptrl)) & CP_REG_FIFO_RPTRL_ADDR_MASK) >> CP_REG_FIFO_RPTRL_ADDR_SHIFT)
556
#define CP_REG_FIFO_RPTRL_SET_ADDR(cp_reg_fifo_rptrl, addr) { \
557
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_RPTRL_ADDR_SIZE)-1))); \
558
cp_reg_fifo_rptrl = (((unsigned long)(cp_reg_fifo_rptrl)) & ~CP_REG_FIFO_RPTRL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_RPTRL_ADDR_SHIFT);\
559
}
560
#define CP_REG_FIFO_RPTRL_TOTAL_SIZE 16
561
#define CP_REG_FIFO_RPTRL(addr) \
562
((((unsigned long)(addr)) << CP_REG_FIFO_RPTRL_ADDR_SHIFT))
563
564
#define CP_REG_FIFO_RPTRH_ADDR_SIZE 13
565
#define CP_REG_FIFO_RPTRH_ADDR_SHIFT 0
566
#define CP_REG_FIFO_RPTRH_ADDR_MASK 0x00001fff
567
#define CP_REG_FIFO_RPTRH_GET_ADDR(cp_reg_fifo_rptrh) \
568
((((unsigned long)(cp_reg_fifo_rptrh)) & CP_REG_FIFO_RPTRH_ADDR_MASK) >> CP_REG_FIFO_RPTRH_ADDR_SHIFT)
569
#define CP_REG_FIFO_RPTRH_SET_ADDR(cp_reg_fifo_rptrh, addr) { \
570
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_RPTRH_ADDR_SIZE)-1))); \
571
cp_reg_fifo_rptrh = (((unsigned long)(cp_reg_fifo_rptrh)) & ~CP_REG_FIFO_RPTRH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_RPTRH_ADDR_SHIFT);\
572
}
573
#define CP_REG_FIFO_RPTRH_TOTAL_SIZE 13
574
#define CP_REG_FIFO_RPTRH(addr) \
575
((((unsigned long)(addr)) << CP_REG_FIFO_RPTRH_ADDR_SHIFT))
576
577
#define CP_REG_FIFO_BRKL_PAD0_SIZE 5
578
#define CP_REG_FIFO_BRKL_PAD0_SHIFT 0
579
#define CP_REG_FIFO_BRKL_PAD0_MASK 0x0000001f
580
#define CP_REG_FIFO_BRKL_GET_PAD0(cp_reg_fifo_brkl) \
581
((((unsigned long)(cp_reg_fifo_brkl)) & CP_REG_FIFO_BRKL_PAD0_MASK) >> CP_REG_FIFO_BRKL_PAD0_SHIFT)
582
#define CP_REG_FIFO_BRKL_SET_PAD0(cp_reg_fifo_brkl, pad0) { \
583
FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_BRKL_PAD0_SIZE)-1))); \
584
cp_reg_fifo_brkl = (((unsigned long)(cp_reg_fifo_brkl)) & ~CP_REG_FIFO_BRKL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_BRKL_PAD0_SHIFT);\
585
}
586
#define CP_REG_FIFO_BRKL_ADDR_SIZE 11
587
#define CP_REG_FIFO_BRKL_ADDR_SHIFT 5
588
#define CP_REG_FIFO_BRKL_ADDR_MASK 0x0000ffe0
589
#define CP_REG_FIFO_BRKL_GET_ADDR(cp_reg_fifo_brkl) \
590
((((unsigned long)(cp_reg_fifo_brkl)) & CP_REG_FIFO_BRKL_ADDR_MASK) >> CP_REG_FIFO_BRKL_ADDR_SHIFT)
591
#define CP_REG_FIFO_BRKL_SET_ADDR(cp_reg_fifo_brkl, addr) { \
592
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_BRKL_ADDR_SIZE)-1))); \
593
cp_reg_fifo_brkl = (((unsigned long)(cp_reg_fifo_brkl)) & ~CP_REG_FIFO_BRKL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_BRKL_ADDR_SHIFT);\
594
}
595
#define CP_REG_FIFO_BRKL_TOTAL_SIZE 16
596
#define CP_REG_FIFO_BRKL(addr) \
597
((((unsigned long)(addr)) << CP_REG_FIFO_BRKL_ADDR_SHIFT))
598
599
/*
600
* cp_reg_fifo_brkh struct
601
*/
602
#define CP_REG_FIFO_BRKH_ADDR_SIZE 13
603
#define CP_REG_FIFO_BRKH_ADDR_SHIFT 0
604
#define CP_REG_FIFO_BRKH_ADDR_MASK 0x00001fff
605
#define CP_REG_FIFO_BRKH_GET_ADDR(cp_reg_fifo_brkh) \
606
((((unsigned long)(cp_reg_fifo_brkh)) & CP_REG_FIFO_BRKH_ADDR_MASK) >> CP_REG_FIFO_BRKH_ADDR_SHIFT)
607
#define CP_REG_FIFO_BRKH_SET_ADDR(cp_reg_fifo_brkh, addr) { \
608
FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_BRKH_ADDR_SIZE)-1))); \
609
cp_reg_fifo_brkh = (((unsigned long)(cp_reg_fifo_brkh)) & ~CP_REG_FIFO_BRKH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_BRKH_ADDR_SHIFT);\
610
}
611
#define CP_REG_FIFO_BRKH_TOTAL_SIZE 13
612
#define CP_REG_FIFO_BRKH(addr) \
613
((((unsigned long)(addr)) << CP_REG_FIFO_BRKH_ADDR_SHIFT))
614
615
/*
616
* memperf_sel enum
617
*/
618
#define MEMPERF_ZERO 0x00000000
619
#define MEMPERF_ONE 0x00000001
620
#define DFIFO_REQ_CNT 0x00000002
621
#define OBJCALL_REQ_CNT 0x00000003
622
#define VCMISS_REQ_CNT 0x00000004
623
#define ALL_MEMREQ_CNT 0x00000005
624
#define MEMPERF_SEL_UNUSED_6 0x00000006
625
#define MEMPERF_SEL_UNUSED_7 0x00000007
626
627
/*
628
* vtx_attr_name value
629
*/
630
#define VTX_ATTR_POSMATIDX 0x00
631
#define VTX_ATTR_TEX0MATIDX 0x01
632
#define VTX_ATTR_TEX1MATIDX 0x02
633
#define VTX_ATTR_TEX2MATIDX 0x03
634
#define VTX_ATTR_TEX3MATIDX 0x04
635
#define VTX_ATTR_TEX4MATIDX 0x05
636
#define VTX_ATTR_TEX5MATIDX 0x06
637
#define VTX_ATTR_TEX6MATIDX 0x07
638
#define VTX_ATTR_TEX7MATIDX 0x08
639
#define VTX_ATTR_POS 0x09
640
#define VTX_ATTR_NRM 0x0a
641
#define VTX_ATTR_COL0 0x0b
642
#define VTX_ATTR_COL1 0x0c
643
#define VTX_ATTR_TEX0 0x0d
644
#define VTX_ATTR_TEX1 0x0e
645
#define VTX_ATTR_TEX2 0x0f
646
#define VTX_ATTR_TEX3 0x10
647
#define VTX_ATTR_TEX4 0x11
648
#define VTX_ATTR_TEX5 0x12
649
#define VTX_ATTR_TEX6 0x13
650
#define VTX_ATTR_TEX7 0x14
651
#define VTX_ATTR_POSARRAY 0x15
652
#define VTX_ATTR_NRMARRAY 0x16
653
#define VTX_ATTR_TEXARRAY 0x17
654
#define VTX_ATTR_LIGHTARRAY 0x18
655
#define VTX_NUM_ATTR 0x19
656
657
/*
658
* vtx_attr_type value
659
*/
660
#define ATTR_NONE 0x0
661
#define ATTR_DIRECT 0x1
662
#define ATTR_INDEX8 0x2
663
#define ATTR_INDEX16 0x3
664
665
/*
666
* attr_comp_fmt value
667
*/
668
#define ATTR_COMP_UBYTE 0x0
669
#define ATTR_COMP_BYTE 0x1
670
#define ATTR_COMP_USHORT 0x2
671
#define ATTR_COMP_SHORT 0x3
672
#define ATTR_COMP_FLOAT 0x4
673
674
/*
675
* attr_clr_fmt value
676
*/
677
#define ATTR_CLR_565 0x0
678
#define ATTR_CLR_888 0x1
679
#define ATTR_CLR_888X 0x2
680
#define ATTR_CLR_4444 0x3
681
#define ATTR_CLR_6666 0x4
682
#define ATTR_CLR_8888 0x5
683
684
/*
685
* cp_vcd_reg_lo struct
686
*/
687
#define CP_VCD_REG_LO_PMIDX_SIZE 1
688
#define CP_VCD_REG_LO_PMIDX_SHIFT 0
689
#define CP_VCD_REG_LO_PMIDX_MASK 0x00000001
690
#define CP_VCD_REG_LO_GET_PMIDX(cp_vcd_reg_lo) \
691
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_PMIDX_MASK) >> CP_VCD_REG_LO_PMIDX_SHIFT)
692
#define CP_VCD_REG_LO_SET_PMIDX(cp_vcd_reg_lo, pmidx) { \
693
FDL_ASSERT(!((pmidx) & ~((1 << CP_VCD_REG_LO_PMIDX_SIZE)-1))); \
694
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_PMIDX_MASK) | (((unsigned long)(pmidx)) << CP_VCD_REG_LO_PMIDX_SHIFT);\
695
}
696
#define CP_VCD_REG_LO_T0MIDX_SIZE 1
697
#define CP_VCD_REG_LO_T0MIDX_SHIFT 1
698
#define CP_VCD_REG_LO_T0MIDX_MASK 0x00000002
699
#define CP_VCD_REG_LO_GET_T0MIDX(cp_vcd_reg_lo) \
700
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T0MIDX_MASK) >> CP_VCD_REG_LO_T0MIDX_SHIFT)
701
#define CP_VCD_REG_LO_SET_T0MIDX(cp_vcd_reg_lo, t0midx) { \
702
FDL_ASSERT(!((t0midx) & ~((1 << CP_VCD_REG_LO_T0MIDX_SIZE)-1))); \
703
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T0MIDX_MASK) | (((unsigned long)(t0midx)) << CP_VCD_REG_LO_T0MIDX_SHIFT);\
704
}
705
#define CP_VCD_REG_LO_T1MIDX_SIZE 1
706
#define CP_VCD_REG_LO_T1MIDX_SHIFT 2
707
#define CP_VCD_REG_LO_T1MIDX_MASK 0x00000004
708
#define CP_VCD_REG_LO_GET_T1MIDX(cp_vcd_reg_lo) \
709
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T1MIDX_MASK) >> CP_VCD_REG_LO_T1MIDX_SHIFT)
710
#define CP_VCD_REG_LO_SET_T1MIDX(cp_vcd_reg_lo, t1midx) { \
711
FDL_ASSERT(!((t1midx) & ~((1 << CP_VCD_REG_LO_T1MIDX_SIZE)-1))); \
712
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T1MIDX_MASK) | (((unsigned long)(t1midx)) << CP_VCD_REG_LO_T1MIDX_SHIFT);\
713
}
714
#define CP_VCD_REG_LO_T2MIDX_SIZE 1
715
#define CP_VCD_REG_LO_T2MIDX_SHIFT 3
716
#define CP_VCD_REG_LO_T2MIDX_MASK 0x00000008
717
#define CP_VCD_REG_LO_GET_T2MIDX(cp_vcd_reg_lo) \
718
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T2MIDX_MASK) >> CP_VCD_REG_LO_T2MIDX_SHIFT)
719
#define CP_VCD_REG_LO_SET_T2MIDX(cp_vcd_reg_lo, t2midx) { \
720
FDL_ASSERT(!((t2midx) & ~((1 << CP_VCD_REG_LO_T2MIDX_SIZE)-1))); \
721
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T2MIDX_MASK) | (((unsigned long)(t2midx)) << CP_VCD_REG_LO_T2MIDX_SHIFT);\
722
}
723
#define CP_VCD_REG_LO_T3MIDX_SIZE 1
724
#define CP_VCD_REG_LO_T3MIDX_SHIFT 4
725
#define CP_VCD_REG_LO_T3MIDX_MASK 0x00000010
726
#define CP_VCD_REG_LO_GET_T3MIDX(cp_vcd_reg_lo) \
727
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T3MIDX_MASK) >> CP_VCD_REG_LO_T3MIDX_SHIFT)
728
#define CP_VCD_REG_LO_SET_T3MIDX(cp_vcd_reg_lo, t3midx) { \
729
FDL_ASSERT(!((t3midx) & ~((1 << CP_VCD_REG_LO_T3MIDX_SIZE)-1))); \
730
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T3MIDX_MASK) | (((unsigned long)(t3midx)) << CP_VCD_REG_LO_T3MIDX_SHIFT);\
731
}
732
#define CP_VCD_REG_LO_T4MIDX_SIZE 1
733
#define CP_VCD_REG_LO_T4MIDX_SHIFT 5
734
#define CP_VCD_REG_LO_T4MIDX_MASK 0x00000020
735
#define CP_VCD_REG_LO_GET_T4MIDX(cp_vcd_reg_lo) \
736
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T4MIDX_MASK) >> CP_VCD_REG_LO_T4MIDX_SHIFT)
737
#define CP_VCD_REG_LO_SET_T4MIDX(cp_vcd_reg_lo, t4midx) { \
738
FDL_ASSERT(!((t4midx) & ~((1 << CP_VCD_REG_LO_T4MIDX_SIZE)-1))); \
739
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T4MIDX_MASK) | (((unsigned long)(t4midx)) << CP_VCD_REG_LO_T4MIDX_SHIFT);\
740
}
741
#define CP_VCD_REG_LO_T5MIDX_SIZE 1
742
#define CP_VCD_REG_LO_T5MIDX_SHIFT 6
743
#define CP_VCD_REG_LO_T5MIDX_MASK 0x00000040
744
#define CP_VCD_REG_LO_GET_T5MIDX(cp_vcd_reg_lo) \
745
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T5MIDX_MASK) >> CP_VCD_REG_LO_T5MIDX_SHIFT)
746
#define CP_VCD_REG_LO_SET_T5MIDX(cp_vcd_reg_lo, t5midx) { \
747
FDL_ASSERT(!((t5midx) & ~((1 << CP_VCD_REG_LO_T5MIDX_SIZE)-1))); \
748
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T5MIDX_MASK) | (((unsigned long)(t5midx)) << CP_VCD_REG_LO_T5MIDX_SHIFT);\
749
}
750
#define CP_VCD_REG_LO_T6MIDX_SIZE 1
751
#define CP_VCD_REG_LO_T6MIDX_SHIFT 7
752
#define CP_VCD_REG_LO_T6MIDX_MASK 0x00000080
753
#define CP_VCD_REG_LO_GET_T6MIDX(cp_vcd_reg_lo) \
754
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T6MIDX_MASK) >> CP_VCD_REG_LO_T6MIDX_SHIFT)
755
#define CP_VCD_REG_LO_SET_T6MIDX(cp_vcd_reg_lo, t6midx) { \
756
FDL_ASSERT(!((t6midx) & ~((1 << CP_VCD_REG_LO_T6MIDX_SIZE)-1))); \
757
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T6MIDX_MASK) | (((unsigned long)(t6midx)) << CP_VCD_REG_LO_T6MIDX_SHIFT);\
758
}
759
#define CP_VCD_REG_LO_T7MIDX_SIZE 1
760
#define CP_VCD_REG_LO_T7MIDX_SHIFT 8
761
#define CP_VCD_REG_LO_T7MIDX_MASK 0x00000100
762
#define CP_VCD_REG_LO_GET_T7MIDX(cp_vcd_reg_lo) \
763
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T7MIDX_MASK) >> CP_VCD_REG_LO_T7MIDX_SHIFT)
764
#define CP_VCD_REG_LO_SET_T7MIDX(cp_vcd_reg_lo, t7midx) { \
765
FDL_ASSERT(!((t7midx) & ~((1 << CP_VCD_REG_LO_T7MIDX_SIZE)-1))); \
766
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T7MIDX_MASK) | (((unsigned long)(t7midx)) << CP_VCD_REG_LO_T7MIDX_SHIFT);\
767
}
768
#define CP_VCD_REG_LO_POS_SIZE 2
769
#define CP_VCD_REG_LO_POS_SHIFT 9
770
#define CP_VCD_REG_LO_POS_MASK 0x00000600
771
#define CP_VCD_REG_LO_GET_POS(cp_vcd_reg_lo) \
772
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_POS_MASK) >> CP_VCD_REG_LO_POS_SHIFT)
773
#define CP_VCD_REG_LO_SET_POS(cp_vcd_reg_lo, pos) { \
774
FDL_ASSERT(!((pos) & ~((1 << CP_VCD_REG_LO_POS_SIZE)-1))); \
775
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_POS_MASK) | (((unsigned long)(pos)) << CP_VCD_REG_LO_POS_SHIFT);\
776
}
777
#define CP_VCD_REG_LO_NRM_SIZE 2
778
#define CP_VCD_REG_LO_NRM_SHIFT 11
779
#define CP_VCD_REG_LO_NRM_MASK 0x00001800
780
#define CP_VCD_REG_LO_GET_NRM(cp_vcd_reg_lo) \
781
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_NRM_MASK) >> CP_VCD_REG_LO_NRM_SHIFT)
782
#define CP_VCD_REG_LO_SET_NRM(cp_vcd_reg_lo, nrm) { \
783
FDL_ASSERT(!((nrm) & ~((1 << CP_VCD_REG_LO_NRM_SIZE)-1))); \
784
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_NRM_MASK) | (((unsigned long)(nrm)) << CP_VCD_REG_LO_NRM_SHIFT);\
785
}
786
#define CP_VCD_REG_LO_COL0_SIZE 2
787
#define CP_VCD_REG_LO_COL0_SHIFT 13
788
#define CP_VCD_REG_LO_COL0_MASK 0x00006000
789
#define CP_VCD_REG_LO_GET_COL0(cp_vcd_reg_lo) \
790
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_COL0_MASK) >> CP_VCD_REG_LO_COL0_SHIFT)
791
#define CP_VCD_REG_LO_SET_COL0(cp_vcd_reg_lo, col0) { \
792
FDL_ASSERT(!((col0) & ~((1 << CP_VCD_REG_LO_COL0_SIZE)-1))); \
793
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_COL0_MASK) | (((unsigned long)(col0)) << CP_VCD_REG_LO_COL0_SHIFT);\
794
}
795
#define CP_VCD_REG_LO_COL1_SIZE 2
796
#define CP_VCD_REG_LO_COL1_SHIFT 15
797
#define CP_VCD_REG_LO_COL1_MASK 0x00018000
798
#define CP_VCD_REG_LO_GET_COL1(cp_vcd_reg_lo) \
799
((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_COL1_MASK) >> CP_VCD_REG_LO_COL1_SHIFT)
800
#define CP_VCD_REG_LO_SET_COL1(cp_vcd_reg_lo, col1) { \
801
FDL_ASSERT(!((col1) & ~((1 << CP_VCD_REG_LO_COL1_SIZE)-1))); \
802
cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_COL1_MASK) | (((unsigned long)(col1)) << CP_VCD_REG_LO_COL1_SHIFT);\
803
}
804
#define CP_VCD_REG_LO_TOTAL_SIZE 17
805
#define CP_VCD_REG_LO(pmidx, t0midx, t1midx, t2midx, t3midx, t4midx, t5midx, t6midx, t7midx, pos, nrm, col0, col1) \
806
((((unsigned long)(pmidx)) << CP_VCD_REG_LO_PMIDX_SHIFT) | \
807
(((unsigned long)(t0midx)) << CP_VCD_REG_LO_T0MIDX_SHIFT) | \
808
(((unsigned long)(t1midx)) << CP_VCD_REG_LO_T1MIDX_SHIFT) | \
809
(((unsigned long)(t2midx)) << CP_VCD_REG_LO_T2MIDX_SHIFT) | \
810
(((unsigned long)(t3midx)) << CP_VCD_REG_LO_T3MIDX_SHIFT) | \
811
(((unsigned long)(t4midx)) << CP_VCD_REG_LO_T4MIDX_SHIFT) | \
812
(((unsigned long)(t5midx)) << CP_VCD_REG_LO_T5MIDX_SHIFT) | \
813
(((unsigned long)(t6midx)) << CP_VCD_REG_LO_T6MIDX_SHIFT) | \
814
(((unsigned long)(t7midx)) << CP_VCD_REG_LO_T7MIDX_SHIFT) | \
815
(((unsigned long)(pos)) << CP_VCD_REG_LO_POS_SHIFT) | \
816
(((unsigned long)(nrm)) << CP_VCD_REG_LO_NRM_SHIFT) | \
817
(((unsigned long)(col0)) << CP_VCD_REG_LO_COL0_SHIFT) | \
818
(((unsigned long)(col1)) << CP_VCD_REG_LO_COL1_SHIFT))
819
820
/*
821
* cp_vcd_reg_hi struct
822
*/
823
#define CP_VCD_REG_HI_TEX0_SIZE 2
824
#define CP_VCD_REG_HI_TEX0_SHIFT 0
825
#define CP_VCD_REG_HI_TEX0_MASK 0x00000003
826
#define CP_VCD_REG_HI_GET_TEX0(cp_vcd_reg_hi) \
827
((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX0_MASK) >> CP_VCD_REG_HI_TEX0_SHIFT)
828
#define CP_VCD_REG_HI_SET_TEX0(cp_vcd_reg_hi, tex0) { \
829
FDL_ASSERT(!((tex0) & ~((1 << CP_VCD_REG_HI_TEX0_SIZE)-1))); \
830
cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX0_MASK) | (((unsigned long)(tex0)) << CP_VCD_REG_HI_TEX0_SHIFT);\
831
}
832
#define CP_VCD_REG_HI_TEX1_SIZE 2
833
#define CP_VCD_REG_HI_TEX1_SHIFT 2
834
#define CP_VCD_REG_HI_TEX1_MASK 0x0000000c
835
#define CP_VCD_REG_HI_GET_TEX1(cp_vcd_reg_hi) \
836
((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX1_MASK) >> CP_VCD_REG_HI_TEX1_SHIFT)
837
#define CP_VCD_REG_HI_SET_TEX1(cp_vcd_reg_hi, tex1) { \
838
FDL_ASSERT(!((tex1) & ~((1 << CP_VCD_REG_HI_TEX1_SIZE)-1))); \
839
cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX1_MASK) | (((unsigned long)(tex1)) << CP_VCD_REG_HI_TEX1_SHIFT);\
840
}
841
#define CP_VCD_REG_HI_TEX2_SIZE 2
842
#define CP_VCD_REG_HI_TEX2_SHIFT 4
843
#define CP_VCD_REG_HI_TEX2_MASK 0x00000030
844
#define CP_VCD_REG_HI_GET_TEX2(cp_vcd_reg_hi) \
845
((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX2_MASK) >> CP_VCD_REG_HI_TEX2_SHIFT)
846
#define CP_VCD_REG_HI_SET_TEX2(cp_vcd_reg_hi, tex2) { \
847
FDL_ASSERT(!((tex2) & ~((1 << CP_VCD_REG_HI_TEX2_SIZE)-1))); \
848
cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX2_MASK) | (((unsigned long)(tex2)) << CP_VCD_REG_HI_TEX2_SHIFT);\
849
}
850
#define CP_VCD_REG_HI_TEX3_SIZE 2
851
#define CP_VCD_REG_HI_TEX3_SHIFT 6
852
#define CP_VCD_REG_HI_TEX3_MASK 0x000000c0
853
#define CP_VCD_REG_HI_GET_TEX3(cp_vcd_reg_hi) \
854
((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX3_MASK) >> CP_VCD_REG_HI_TEX3_SHIFT)
855
#define CP_VCD_REG_HI_SET_TEX3(cp_vcd_reg_hi, tex3) { \
856
FDL_ASSERT(!((tex3) & ~((1 << CP_VCD_REG_HI_TEX3_SIZE)-1))); \
857
cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX3_MASK) | (((unsigned long)(tex3)) << CP_VCD_REG_HI_TEX3_SHIFT);\
858
}
859
#define CP_VCD_REG_HI_TEX4_SIZE 2
860
#define CP_VCD_REG_HI_TEX4_SHIFT 8
861
#define CP_VCD_REG_HI_TEX4_MASK 0x00000300
862
#define CP_VCD_REG_HI_GET_TEX4(cp_vcd_reg_hi) \
863
((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX4_MASK) >> CP_VCD_REG_HI_TEX4_SHIFT)
864
#define CP_VCD_REG_HI_SET_TEX4(cp_vcd_reg_hi, tex4) { \
865
FDL_ASSERT(!((tex4) & ~((1 << CP_VCD_REG_HI_TEX4_SIZE)-1))); \
866
cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX4_MASK) | (((unsigned long)(tex4)) << CP_VCD_REG_HI_TEX4_SHIFT);\
867
}
868
#define CP_VCD_REG_HI_TEX5_SIZE 2
869
#define CP_VCD_REG_HI_TEX5_SHIFT 10
870
#define CP_VCD_REG_HI_TEX5_MASK 0x00000c00
871
#define CP_VCD_REG_HI_GET_TEX5(cp_vcd_reg_hi) \
872
((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX5_MASK) >> CP_VCD_REG_HI_TEX5_SHIFT)
873
#define CP_VCD_REG_HI_SET_TEX5(cp_vcd_reg_hi, tex5) { \
874
FDL_ASSERT(!((tex5) & ~((1 << CP_VCD_REG_HI_TEX5_SIZE)-1))); \
875
cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX5_MASK) | (((unsigned long)(tex5)) << CP_VCD_REG_HI_TEX5_SHIFT);\
876
}
877
#define CP_VCD_REG_HI_TEX6_SIZE 2
878
#define CP_VCD_REG_HI_TEX6_SHIFT 12
879
#define CP_VCD_REG_HI_TEX6_MASK 0x00003000
880
#define CP_VCD_REG_HI_GET_TEX6(cp_vcd_reg_hi) \
881
((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX6_MASK) >> CP_VCD_REG_HI_TEX6_SHIFT)
882
#define CP_VCD_REG_HI_SET_TEX6(cp_vcd_reg_hi, tex6) { \
883
FDL_ASSERT(!((tex6) & ~((1 << CP_VCD_REG_HI_TEX6_SIZE)-1))); \
884
cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX6_MASK) | (((unsigned long)(tex6)) << CP_VCD_REG_HI_TEX6_SHIFT);\
885
}
886
#define CP_VCD_REG_HI_TEX7_SIZE 2
887
#define CP_VCD_REG_HI_TEX7_SHIFT 14
888
#define CP_VCD_REG_HI_TEX7_MASK 0x0000c000
889
#define CP_VCD_REG_HI_GET_TEX7(cp_vcd_reg_hi) \
890
((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX7_MASK) >> CP_VCD_REG_HI_TEX7_SHIFT)
891
#define CP_VCD_REG_HI_SET_TEX7(cp_vcd_reg_hi, tex7) { \
892
FDL_ASSERT(!((tex7) & ~((1 << CP_VCD_REG_HI_TEX7_SIZE)-1))); \
893
cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX7_MASK) | (((unsigned long)(tex7)) << CP_VCD_REG_HI_TEX7_SHIFT);\
894
}
895
#define CP_VCD_REG_HI_TOTAL_SIZE 16
896
#define CP_VCD_REG_HI(tex0, tex1, tex2, tex3, tex4, tex5, tex6, tex7) \
897
((((unsigned long)(tex0)) << CP_VCD_REG_HI_TEX0_SHIFT) | \
898
(((unsigned long)(tex1)) << CP_VCD_REG_HI_TEX1_SHIFT) | \
899
(((unsigned long)(tex2)) << CP_VCD_REG_HI_TEX2_SHIFT) | \
900
(((unsigned long)(tex3)) << CP_VCD_REG_HI_TEX3_SHIFT) | \
901
(((unsigned long)(tex4)) << CP_VCD_REG_HI_TEX4_SHIFT) | \
902
(((unsigned long)(tex5)) << CP_VCD_REG_HI_TEX5_SHIFT) | \
903
(((unsigned long)(tex6)) << CP_VCD_REG_HI_TEX6_SHIFT) | \
904
(((unsigned long)(tex7)) << CP_VCD_REG_HI_TEX7_SHIFT))
905
906
/*
907
* cp_vat_table value
908
*/
909
#define CP_NUM_VATS 0x08
910
911
/*
912
* cp_vat_reg_a struct
913
*/
914
#define CP_VAT_REG_A_POSCNT_SIZE 1
915
#define CP_VAT_REG_A_POSCNT_SHIFT 0
916
#define CP_VAT_REG_A_POSCNT_MASK 0x00000001
917
#define CP_VAT_REG_A_GET_POSCNT(cp_vat_reg_a) \
918
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_POSCNT_MASK) >> CP_VAT_REG_A_POSCNT_SHIFT)
919
#define CP_VAT_REG_A_SET_POSCNT(cp_vat_reg_a, posCnt) { \
920
FDL_ASSERT(!((posCnt) & ~((1 << CP_VAT_REG_A_POSCNT_SIZE)-1))); \
921
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_POSCNT_MASK) | (((unsigned long)(posCnt)) << CP_VAT_REG_A_POSCNT_SHIFT);\
922
}
923
#define CP_VAT_REG_A_POSFMT_SIZE 3
924
#define CP_VAT_REG_A_POSFMT_SHIFT 1
925
#define CP_VAT_REG_A_POSFMT_MASK 0x0000000e
926
#define CP_VAT_REG_A_GET_POSFMT(cp_vat_reg_a) \
927
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_POSFMT_MASK) >> CP_VAT_REG_A_POSFMT_SHIFT)
928
#define CP_VAT_REG_A_SET_POSFMT(cp_vat_reg_a, posFmt) { \
929
FDL_ASSERT(!((posFmt) & ~((1 << CP_VAT_REG_A_POSFMT_SIZE)-1))); \
930
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_POSFMT_MASK) | (((unsigned long)(posFmt)) << CP_VAT_REG_A_POSFMT_SHIFT);\
931
}
932
#define CP_VAT_REG_A_POSSHFT_SIZE 5
933
#define CP_VAT_REG_A_POSSHFT_SHIFT 4
934
#define CP_VAT_REG_A_POSSHFT_MASK 0x000001f0
935
#define CP_VAT_REG_A_GET_POSSHFT(cp_vat_reg_a) \
936
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_POSSHFT_MASK) >> CP_VAT_REG_A_POSSHFT_SHIFT)
937
#define CP_VAT_REG_A_SET_POSSHFT(cp_vat_reg_a, posShft) { \
938
FDL_ASSERT(!((posShft) & ~((1 << CP_VAT_REG_A_POSSHFT_SIZE)-1))); \
939
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_POSSHFT_MASK) | (((unsigned long)(posShft)) << CP_VAT_REG_A_POSSHFT_SHIFT);\
940
}
941
#define CP_VAT_REG_A_NRMCNT_SIZE 1
942
#define CP_VAT_REG_A_NRMCNT_SHIFT 9
943
#define CP_VAT_REG_A_NRMCNT_MASK 0x00000200
944
#define CP_VAT_REG_A_GET_NRMCNT(cp_vat_reg_a) \
945
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_NRMCNT_MASK) >> CP_VAT_REG_A_NRMCNT_SHIFT)
946
#define CP_VAT_REG_A_SET_NRMCNT(cp_vat_reg_a, nrmCnt) { \
947
FDL_ASSERT(!((nrmCnt) & ~((1 << CP_VAT_REG_A_NRMCNT_SIZE)-1))); \
948
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_NRMCNT_MASK) | (((unsigned long)(nrmCnt)) << CP_VAT_REG_A_NRMCNT_SHIFT);\
949
}
950
#define CP_VAT_REG_A_NRMFMT_SIZE 3
951
#define CP_VAT_REG_A_NRMFMT_SHIFT 10
952
#define CP_VAT_REG_A_NRMFMT_MASK 0x00001c00
953
#define CP_VAT_REG_A_GET_NRMFMT(cp_vat_reg_a) \
954
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_NRMFMT_MASK) >> CP_VAT_REG_A_NRMFMT_SHIFT)
955
#define CP_VAT_REG_A_SET_NRMFMT(cp_vat_reg_a, nrmFmt) { \
956
FDL_ASSERT(!((nrmFmt) & ~((1 << CP_VAT_REG_A_NRMFMT_SIZE)-1))); \
957
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_NRMFMT_MASK) | (((unsigned long)(nrmFmt)) << CP_VAT_REG_A_NRMFMT_SHIFT);\
958
}
959
#define CP_VAT_REG_A_COL0CNT_SIZE 1
960
#define CP_VAT_REG_A_COL0CNT_SHIFT 13
961
#define CP_VAT_REG_A_COL0CNT_MASK 0x00002000
962
#define CP_VAT_REG_A_GET_COL0CNT(cp_vat_reg_a) \
963
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_COL0CNT_MASK) >> CP_VAT_REG_A_COL0CNT_SHIFT)
964
#define CP_VAT_REG_A_SET_COL0CNT(cp_vat_reg_a, Col0Cnt) { \
965
FDL_ASSERT(!((Col0Cnt) & ~((1 << CP_VAT_REG_A_COL0CNT_SIZE)-1))); \
966
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_COL0CNT_MASK) | (((unsigned long)(Col0Cnt)) << CP_VAT_REG_A_COL0CNT_SHIFT);\
967
}
968
#define CP_VAT_REG_A_COL0FMT_SIZE 3
969
#define CP_VAT_REG_A_COL0FMT_SHIFT 14
970
#define CP_VAT_REG_A_COL0FMT_MASK 0x0001c000
971
#define CP_VAT_REG_A_GET_COL0FMT(cp_vat_reg_a) \
972
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_COL0FMT_MASK) >> CP_VAT_REG_A_COL0FMT_SHIFT)
973
#define CP_VAT_REG_A_SET_COL0FMT(cp_vat_reg_a, Col0Fmt) { \
974
FDL_ASSERT(!((Col0Fmt) & ~((1 << CP_VAT_REG_A_COL0FMT_SIZE)-1))); \
975
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_COL0FMT_MASK) | (((unsigned long)(Col0Fmt)) << CP_VAT_REG_A_COL0FMT_SHIFT);\
976
}
977
#define CP_VAT_REG_A_COL1CNT_SIZE 1
978
#define CP_VAT_REG_A_COL1CNT_SHIFT 17
979
#define CP_VAT_REG_A_COL1CNT_MASK 0x00020000
980
#define CP_VAT_REG_A_GET_COL1CNT(cp_vat_reg_a) \
981
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_COL1CNT_MASK) >> CP_VAT_REG_A_COL1CNT_SHIFT)
982
#define CP_VAT_REG_A_SET_COL1CNT(cp_vat_reg_a, Col1Cnt) { \
983
FDL_ASSERT(!((Col1Cnt) & ~((1 << CP_VAT_REG_A_COL1CNT_SIZE)-1))); \
984
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_COL1CNT_MASK) | (((unsigned long)(Col1Cnt)) << CP_VAT_REG_A_COL1CNT_SHIFT);\
985
}
986
#define CP_VAT_REG_A_COL1FMT_SIZE 3
987
#define CP_VAT_REG_A_COL1FMT_SHIFT 18
988
#define CP_VAT_REG_A_COL1FMT_MASK 0x001c0000
989
#define CP_VAT_REG_A_GET_COL1FMT(cp_vat_reg_a) \
990
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_COL1FMT_MASK) >> CP_VAT_REG_A_COL1FMT_SHIFT)
991
#define CP_VAT_REG_A_SET_COL1FMT(cp_vat_reg_a, Col1Fmt) { \
992
FDL_ASSERT(!((Col1Fmt) & ~((1 << CP_VAT_REG_A_COL1FMT_SIZE)-1))); \
993
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_COL1FMT_MASK) | (((unsigned long)(Col1Fmt)) << CP_VAT_REG_A_COL1FMT_SHIFT);\
994
}
995
#define CP_VAT_REG_A_TEX0CNT_SIZE 1
996
#define CP_VAT_REG_A_TEX0CNT_SHIFT 21
997
#define CP_VAT_REG_A_TEX0CNT_MASK 0x00200000
998
#define CP_VAT_REG_A_GET_TEX0CNT(cp_vat_reg_a) \
999
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_TEX0CNT_MASK) >> CP_VAT_REG_A_TEX0CNT_SHIFT)
1000
#define CP_VAT_REG_A_SET_TEX0CNT(cp_vat_reg_a, tex0Cnt) { \
1001
FDL_ASSERT(!((tex0Cnt) & ~((1 << CP_VAT_REG_A_TEX0CNT_SIZE)-1))); \
1002
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_TEX0CNT_MASK) | (((unsigned long)(tex0Cnt)) << CP_VAT_REG_A_TEX0CNT_SHIFT);\
1003
}
1004
#define CP_VAT_REG_A_TEX0FMT_SIZE 3
1005
#define CP_VAT_REG_A_TEX0FMT_SHIFT 22
1006
#define CP_VAT_REG_A_TEX0FMT_MASK 0x01c00000
1007
#define CP_VAT_REG_A_GET_TEX0FMT(cp_vat_reg_a) \
1008
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_TEX0FMT_MASK) >> CP_VAT_REG_A_TEX0FMT_SHIFT)
1009
#define CP_VAT_REG_A_SET_TEX0FMT(cp_vat_reg_a, tex0Fmt) { \
1010
FDL_ASSERT(!((tex0Fmt) & ~((1 << CP_VAT_REG_A_TEX0FMT_SIZE)-1))); \
1011
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_TEX0FMT_MASK) | (((unsigned long)(tex0Fmt)) << CP_VAT_REG_A_TEX0FMT_SHIFT);\
1012
}
1013
#define CP_VAT_REG_A_TEX0SHFT_SIZE 5
1014
#define CP_VAT_REG_A_TEX0SHFT_SHIFT 25
1015
#define CP_VAT_REG_A_TEX0SHFT_MASK 0x3e000000
1016
#define CP_VAT_REG_A_GET_TEX0SHFT(cp_vat_reg_a) \
1017
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_TEX0SHFT_MASK) >> CP_VAT_REG_A_TEX0SHFT_SHIFT)
1018
#define CP_VAT_REG_A_SET_TEX0SHFT(cp_vat_reg_a, tex0Shft) { \
1019
FDL_ASSERT(!((tex0Shft) & ~((1 << CP_VAT_REG_A_TEX0SHFT_SIZE)-1))); \
1020
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_TEX0SHFT_MASK) | (((unsigned long)(tex0Shft)) << CP_VAT_REG_A_TEX0SHFT_SHIFT);\
1021
}
1022
#define CP_VAT_REG_A_BYTEDEQUANT_SIZE 1
1023
#define CP_VAT_REG_A_BYTEDEQUANT_SHIFT 30
1024
#define CP_VAT_REG_A_BYTEDEQUANT_MASK 0x40000000
1025
#define CP_VAT_REG_A_GET_BYTEDEQUANT(cp_vat_reg_a) \
1026
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_BYTEDEQUANT_MASK) >> CP_VAT_REG_A_BYTEDEQUANT_SHIFT)
1027
#define CP_VAT_REG_A_SET_BYTEDEQUANT(cp_vat_reg_a, byteDequant) { \
1028
FDL_ASSERT(!((byteDequant) & ~((1 << CP_VAT_REG_A_BYTEDEQUANT_SIZE)-1))); \
1029
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_BYTEDEQUANT_MASK) | (((unsigned long)(byteDequant)) << CP_VAT_REG_A_BYTEDEQUANT_SHIFT);\
1030
}
1031
#define CP_VAT_REG_A_NORMALINDEX3_SIZE 1
1032
#define CP_VAT_REG_A_NORMALINDEX3_SHIFT 31
1033
#define CP_VAT_REG_A_NORMALINDEX3_MASK 0x80000000
1034
#define CP_VAT_REG_A_GET_NORMALINDEX3(cp_vat_reg_a) \
1035
((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_NORMALINDEX3_MASK) >> CP_VAT_REG_A_NORMALINDEX3_SHIFT)
1036
#define CP_VAT_REG_A_SET_NORMALINDEX3(cp_vat_reg_a, normalIndex3) { \
1037
FDL_ASSERT(!((normalIndex3) & ~((1 << CP_VAT_REG_A_NORMALINDEX3_SIZE)-1))); \
1038
cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_NORMALINDEX3_MASK) | (((unsigned long)(normalIndex3)) << CP_VAT_REG_A_NORMALINDEX3_SHIFT);\
1039
}
1040
#define CP_VAT_REG_A_TOTAL_SIZE 32
1041
#define CP_VAT_REG_A(posCnt, posFmt, posShft, nrmCnt, nrmFmt, Col0Cnt, Col0Fmt, Col1Cnt, Col1Fmt, tex0Cnt, tex0Fmt, tex0Shft, byteDequant, normalIndex3) \
1042
((((unsigned long)(posCnt)) << CP_VAT_REG_A_POSCNT_SHIFT) | \
1043
(((unsigned long)(posFmt)) << CP_VAT_REG_A_POSFMT_SHIFT) | \
1044
(((unsigned long)(posShft)) << CP_VAT_REG_A_POSSHFT_SHIFT) | \
1045
(((unsigned long)(nrmCnt)) << CP_VAT_REG_A_NRMCNT_SHIFT) | \
1046
(((unsigned long)(nrmFmt)) << CP_VAT_REG_A_NRMFMT_SHIFT) | \
1047
(((unsigned long)(Col0Cnt)) << CP_VAT_REG_A_COL0CNT_SHIFT) | \
1048
(((unsigned long)(Col0Fmt)) << CP_VAT_REG_A_COL0FMT_SHIFT) | \
1049
(((unsigned long)(Col1Cnt)) << CP_VAT_REG_A_COL1CNT_SHIFT) | \
1050
(((unsigned long)(Col1Fmt)) << CP_VAT_REG_A_COL1FMT_SHIFT) | \
1051
(((unsigned long)(tex0Cnt)) << CP_VAT_REG_A_TEX0CNT_SHIFT) | \
1052
(((unsigned long)(tex0Fmt)) << CP_VAT_REG_A_TEX0FMT_SHIFT) | \
1053
(((unsigned long)(tex0Shft)) << CP_VAT_REG_A_TEX0SHFT_SHIFT) | \
1054
(((unsigned long)(byteDequant)) << CP_VAT_REG_A_BYTEDEQUANT_SHIFT) | \
1055
(((unsigned long)(normalIndex3)) << CP_VAT_REG_A_NORMALINDEX3_SHIFT))
1056
1057
/*
1058
* cp_vat_reg_b struct
1059
*/
1060
#define CP_VAT_REG_B_TEX1CNT_SIZE 1
1061
#define CP_VAT_REG_B_TEX1CNT_SHIFT 0
1062
#define CP_VAT_REG_B_TEX1CNT_MASK 0x00000001
1063
#define CP_VAT_REG_B_GET_TEX1CNT(cp_vat_reg_b) \
1064
((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX1CNT_MASK) >> CP_VAT_REG_B_TEX1CNT_SHIFT)
1065
#define CP_VAT_REG_B_SET_TEX1CNT(cp_vat_reg_b, tex1Cnt) { \
1066
FDL_ASSERT(!((tex1Cnt) & ~((1 << CP_VAT_REG_B_TEX1CNT_SIZE)-1))); \
1067
cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX1CNT_MASK) | (((unsigned long)(tex1Cnt)) << CP_VAT_REG_B_TEX1CNT_SHIFT);\
1068
}
1069
#define CP_VAT_REG_B_TEX1FMT_SIZE 3
1070
#define CP_VAT_REG_B_TEX1FMT_SHIFT 1
1071
#define CP_VAT_REG_B_TEX1FMT_MASK 0x0000000e
1072
#define CP_VAT_REG_B_GET_TEX1FMT(cp_vat_reg_b) \
1073
((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX1FMT_MASK) >> CP_VAT_REG_B_TEX1FMT_SHIFT)
1074
#define CP_VAT_REG_B_SET_TEX1FMT(cp_vat_reg_b, tex1Fmt) { \
1075
FDL_ASSERT(!((tex1Fmt) & ~((1 << CP_VAT_REG_B_TEX1FMT_SIZE)-1))); \
1076
cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX1FMT_MASK) | (((unsigned long)(tex1Fmt)) << CP_VAT_REG_B_TEX1FMT_SHIFT);\
1077
}
1078
#define CP_VAT_REG_B_TEX1SHFT_SIZE 5
1079
#define CP_VAT_REG_B_TEX1SHFT_SHIFT 4
1080
#define CP_VAT_REG_B_TEX1SHFT_MASK 0x000001f0
1081
#define CP_VAT_REG_B_GET_TEX1SHFT(cp_vat_reg_b) \
1082
((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX1SHFT_MASK) >> CP_VAT_REG_B_TEX1SHFT_SHIFT)
1083
#define CP_VAT_REG_B_SET_TEX1SHFT(cp_vat_reg_b, tex1Shft) { \
1084
FDL_ASSERT(!((tex1Shft) & ~((1 << CP_VAT_REG_B_TEX1SHFT_SIZE)-1))); \
1085
cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX1SHFT_MASK) | (((unsigned long)(tex1Shft)) << CP_VAT_REG_B_TEX1SHFT_SHIFT);\
1086
}
1087
#define CP_VAT_REG_B_TEX2CNT_SIZE 1
1088
#define CP_VAT_REG_B_TEX2CNT_SHIFT 9
1089
#define CP_VAT_REG_B_TEX2CNT_MASK 0x00000200
1090
#define CP_VAT_REG_B_GET_TEX2CNT(cp_vat_reg_b) \
1091
((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX2CNT_MASK) >> CP_VAT_REG_B_TEX2CNT_SHIFT)
1092
#define CP_VAT_REG_B_SET_TEX2CNT(cp_vat_reg_b, tex2Cnt) { \
1093
FDL_ASSERT(!((tex2Cnt) & ~((1 << CP_VAT_REG_B_TEX2CNT_SIZE)-1))); \
1094
cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX2CNT_MASK) | (((unsigned long)(tex2Cnt)) << CP_VAT_REG_B_TEX2CNT_SHIFT);\
1095
}
1096
#define CP_VAT_REG_B_TEX2FMT_SIZE 3
1097
#define CP_VAT_REG_B_TEX2FMT_SHIFT 10
1098
#define CP_VAT_REG_B_TEX2FMT_MASK 0x00001c00
1099
#define CP_VAT_REG_B_GET_TEX2FMT(cp_vat_reg_b) \
1100
((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX2FMT_MASK) >> CP_VAT_REG_B_TEX2FMT_SHIFT)
1101
#define CP_VAT_REG_B_SET_TEX2FMT(cp_vat_reg_b, tex2Fmt) { \
1102
FDL_ASSERT(!((tex2Fmt) & ~((1 << CP_VAT_REG_B_TEX2FMT_SIZE)-1))); \
1103
cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX2FMT_MASK) | (((unsigned long)(tex2Fmt)) << CP_VAT_REG_B_TEX2FMT_SHIFT);\
1104
}
1105
#define CP_VAT_REG_B_TEX2SHFT_SIZE 5
1106
#define CP_VAT_REG_B_TEX2SHFT_SHIFT 13
1107
#define CP_VAT_REG_B_TEX2SHFT_MASK 0x0003e000
1108
#define CP_VAT_REG_B_GET_TEX2SHFT(cp_vat_reg_b) \
1109
((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX2SHFT_MASK) >> CP_VAT_REG_B_TEX2SHFT_SHIFT)
1110
#define CP_VAT_REG_B_SET_TEX2SHFT(cp_vat_reg_b, tex2Shft) { \
1111
FDL_ASSERT(!((tex2Shft) & ~((1 << CP_VAT_REG_B_TEX2SHFT_SIZE)-1))); \
1112
cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX2SHFT_MASK) | (((unsigned long)(tex2Shft)) << CP_VAT_REG_B_TEX2SHFT_SHIFT);\
1113
}
1114
#define CP_VAT_REG_B_TEX3CNT_SIZE 1
1115
#define CP_VAT_REG_B_TEX3CNT_SHIFT 18
1116
#define CP_VAT_REG_B_TEX3CNT_MASK 0x00040000
1117
#define CP_VAT_REG_B_GET_TEX3CNT(cp_vat_reg_b) \
1118
((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX3CNT_MASK) >> CP_VAT_REG_B_TEX3CNT_SHIFT)
1119
#define CP_VAT_REG_B_SET_TEX3CNT(cp_vat_reg_b, tex3Cnt) { \
1120
FDL_ASSERT(!((tex3Cnt) & ~((1 << CP_VAT_REG_B_TEX3CNT_SIZE)-1))); \
1121
cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX3CNT_MASK) | (((unsigned long)(tex3Cnt)) << CP_VAT_REG_B_TEX3CNT_SHIFT);\
1122
}
1123
#define CP_VAT_REG_B_TEX3FMT_SIZE 3
1124
#define CP_VAT_REG_B_TEX3FMT_SHIFT 19
1125
#define CP_VAT_REG_B_TEX3FMT_MASK 0x00380000
1126
#define CP_VAT_REG_B_GET_TEX3FMT(cp_vat_reg_b) \
1127
((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX3FMT_MASK) >> CP_VAT_REG_B_TEX3FMT_SHIFT)
1128
#define CP_VAT_REG_B_SET_TEX3FMT(cp_vat_reg_b, tex3Fmt) { \
1129
FDL_ASSERT(!((tex3Fmt) & ~((1 << CP_VAT_REG_B_TEX3FMT_SIZE)-1))); \
1130
cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX3FMT_MASK) | (((unsigned long)(tex3Fmt)) << CP_VAT_REG_B_TEX3FMT_SHIFT);\
1131
}
1132
#define CP_VAT_REG_B_TEX3SHFT_SIZE 5
1133
#define CP_VAT_REG_B_TEX3SHFT_SHIFT 22
1134
#define CP_VAT_REG_B_TEX3SHFT_MASK 0x07c00000
1135
#define CP_VAT_REG_B_GET_TEX3SHFT(cp_vat_reg_b) \
1136
((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX3SHFT_MASK) >> CP_VAT_REG_B_TEX3SHFT_SHIFT)
1137
#define CP_VAT_REG_B_SET_TEX3SHFT(cp_vat_reg_b, tex3Shft) { \
1138
FDL_ASSERT(!((tex3Shft) & ~((1 << CP_VAT_REG_B_TEX3SHFT_SIZE)-1))); \
1139
cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX3SHFT_MASK) | (((unsigned long)(tex3Shft)) << CP_VAT_REG_B_TEX3SHFT_SHIFT);\
1140
}
1141
#define CP_VAT_REG_B_TEX4CNT_SIZE 1
1142
#define CP_VAT_REG_B_TEX4CNT_SHIFT 27
1143
#define CP_VAT_REG_B_TEX4CNT_MASK 0x08000000
1144
#define CP_VAT_REG_B_GET_TEX4CNT(cp_vat_reg_b) \
1145
((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX4CNT_MASK) >> CP_VAT_REG_B_TEX4CNT_SHIFT)
1146
#define CP_VAT_REG_B_SET_TEX4CNT(cp_vat_reg_b, tex4Cnt) { \
1147
FDL_ASSERT(!((tex4Cnt) & ~((1 << CP_VAT_REG_B_TEX4CNT_SIZE)-1))); \
1148
cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX4CNT_MASK) | (((unsigned long)(tex4Cnt)) << CP_VAT_REG_B_TEX4CNT_SHIFT);\
1149
}
1150
#define CP_VAT_REG_B_TEX4FMT_SIZE 3
1151
#define CP_VAT_REG_B_TEX4FMT_SHIFT 28
1152
#define CP_VAT_REG_B_TEX4FMT_MASK 0x70000000
1153
#define CP_VAT_REG_B_GET_TEX4FMT(cp_vat_reg_b) \
1154
((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX4FMT_MASK) >> CP_VAT_REG_B_TEX4FMT_SHIFT)
1155
#define CP_VAT_REG_B_SET_TEX4FMT(cp_vat_reg_b, tex4Fmt) { \
1156
FDL_ASSERT(!((tex4Fmt) & ~((1 << CP_VAT_REG_B_TEX4FMT_SIZE)-1))); \
1157
cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX4FMT_MASK) | (((unsigned long)(tex4Fmt)) << CP_VAT_REG_B_TEX4FMT_SHIFT);\
1158
}
1159
#define CP_VAT_REG_B_VCACHE_ENHANCE_SIZE 1
1160
#define CP_VAT_REG_B_VCACHE_ENHANCE_SHIFT 31
1161
#define CP_VAT_REG_B_VCACHE_ENHANCE_MASK 0x80000000
1162
#define CP_VAT_REG_B_GET_VCACHE_ENHANCE(cp_vat_reg_b) \
1163
((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_VCACHE_ENHANCE_MASK) >> CP_VAT_REG_B_VCACHE_ENHANCE_SHIFT)
1164
#define CP_VAT_REG_B_SET_VCACHE_ENHANCE(cp_vat_reg_b, vcache_enhance) { \
1165
FDL_ASSERT(!((vcache_enhance) & ~((1 << CP_VAT_REG_B_VCACHE_ENHANCE_SIZE)-1))); \
1166
cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_VCACHE_ENHANCE_MASK) | (((unsigned long)(vcache_enhance)) << CP_VAT_REG_B_VCACHE_ENHANCE_SHIFT);\
1167
}
1168
#define CP_VAT_REG_B_TOTAL_SIZE 32
1169
#define CP_VAT_REG_B(tex1Cnt, tex1Fmt, tex1Shft, tex2Cnt, tex2Fmt, tex2Shft, tex3Cnt, tex3Fmt, tex3Shft, tex4Cnt, tex4Fmt, vcache_enhance) \
1170
((((unsigned long)(tex1Cnt)) << CP_VAT_REG_B_TEX1CNT_SHIFT) | \
1171
(((unsigned long)(tex1Fmt)) << CP_VAT_REG_B_TEX1FMT_SHIFT) | \
1172
(((unsigned long)(tex1Shft)) << CP_VAT_REG_B_TEX1SHFT_SHIFT) | \
1173
(((unsigned long)(tex2Cnt)) << CP_VAT_REG_B_TEX2CNT_SHIFT) | \
1174
(((unsigned long)(tex2Fmt)) << CP_VAT_REG_B_TEX2FMT_SHIFT) | \
1175
(((unsigned long)(tex2Shft)) << CP_VAT_REG_B_TEX2SHFT_SHIFT) | \
1176
(((unsigned long)(tex3Cnt)) << CP_VAT_REG_B_TEX3CNT_SHIFT) | \
1177
(((unsigned long)(tex3Fmt)) << CP_VAT_REG_B_TEX3FMT_SHIFT) | \
1178
(((unsigned long)(tex3Shft)) << CP_VAT_REG_B_TEX3SHFT_SHIFT) | \
1179
(((unsigned long)(tex4Cnt)) << CP_VAT_REG_B_TEX4CNT_SHIFT) | \
1180
(((unsigned long)(tex4Fmt)) << CP_VAT_REG_B_TEX4FMT_SHIFT) | \
1181
(((unsigned long)(vcache_enhance)) << CP_VAT_REG_B_VCACHE_ENHANCE_SHIFT))
1182
1183
/*
1184
* cp_vat_reg_c struct
1185
*/
1186
#define CP_VAT_REG_C_TEX4SHFT_SIZE 5
1187
#define CP_VAT_REG_C_TEX4SHFT_SHIFT 0
1188
#define CP_VAT_REG_C_TEX4SHFT_MASK 0x0000001f
1189
#define CP_VAT_REG_C_GET_TEX4SHFT(cp_vat_reg_c) \
1190
((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX4SHFT_MASK) >> CP_VAT_REG_C_TEX4SHFT_SHIFT)
1191
#define CP_VAT_REG_C_SET_TEX4SHFT(cp_vat_reg_c, tex4Shft) { \
1192
FDL_ASSERT(!((tex4Shft) & ~((1 << CP_VAT_REG_C_TEX4SHFT_SIZE)-1))); \
1193
cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX4SHFT_MASK) | (((unsigned long)(tex4Shft)) << CP_VAT_REG_C_TEX4SHFT_SHIFT);\
1194
}
1195
#define CP_VAT_REG_C_TEX5CNT_SIZE 1
1196
#define CP_VAT_REG_C_TEX5CNT_SHIFT 5
1197
#define CP_VAT_REG_C_TEX5CNT_MASK 0x00000020
1198
#define CP_VAT_REG_C_GET_TEX5CNT(cp_vat_reg_c) \
1199
((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX5CNT_MASK) >> CP_VAT_REG_C_TEX5CNT_SHIFT)
1200
#define CP_VAT_REG_C_SET_TEX5CNT(cp_vat_reg_c, tex5Cnt) { \
1201
FDL_ASSERT(!((tex5Cnt) & ~((1 << CP_VAT_REG_C_TEX5CNT_SIZE)-1))); \
1202
cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX5CNT_MASK) | (((unsigned long)(tex5Cnt)) << CP_VAT_REG_C_TEX5CNT_SHIFT);\
1203
}
1204
#define CP_VAT_REG_C_TEX5FMT_SIZE 3
1205
#define CP_VAT_REG_C_TEX5FMT_SHIFT 6
1206
#define CP_VAT_REG_C_TEX5FMT_MASK 0x000001c0
1207
#define CP_VAT_REG_C_GET_TEX5FMT(cp_vat_reg_c) \
1208
((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX5FMT_MASK) >> CP_VAT_REG_C_TEX5FMT_SHIFT)
1209
#define CP_VAT_REG_C_SET_TEX5FMT(cp_vat_reg_c, tex5Fmt) { \
1210
FDL_ASSERT(!((tex5Fmt) & ~((1 << CP_VAT_REG_C_TEX5FMT_SIZE)-1))); \
1211
cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX5FMT_MASK) | (((unsigned long)(tex5Fmt)) << CP_VAT_REG_C_TEX5FMT_SHIFT);\
1212
}
1213
#define CP_VAT_REG_C_TEX5SHFT_SIZE 5
1214
#define CP_VAT_REG_C_TEX5SHFT_SHIFT 9
1215
#define CP_VAT_REG_C_TEX5SHFT_MASK 0x00003e00
1216
#define CP_VAT_REG_C_GET_TEX5SHFT(cp_vat_reg_c) \
1217
((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX5SHFT_MASK) >> CP_VAT_REG_C_TEX5SHFT_SHIFT)
1218
#define CP_VAT_REG_C_SET_TEX5SHFT(cp_vat_reg_c, tex5Shft) { \
1219
FDL_ASSERT(!((tex5Shft) & ~((1 << CP_VAT_REG_C_TEX5SHFT_SIZE)-1))); \
1220
cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX5SHFT_MASK) | (((unsigned long)(tex5Shft)) << CP_VAT_REG_C_TEX5SHFT_SHIFT);\
1221
}
1222
#define CP_VAT_REG_C_TEX6CNT_SIZE 1
1223
#define CP_VAT_REG_C_TEX6CNT_SHIFT 14
1224
#define CP_VAT_REG_C_TEX6CNT_MASK 0x00004000
1225
#define CP_VAT_REG_C_GET_TEX6CNT(cp_vat_reg_c) \
1226
((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX6CNT_MASK) >> CP_VAT_REG_C_TEX6CNT_SHIFT)
1227
#define CP_VAT_REG_C_SET_TEX6CNT(cp_vat_reg_c, tex6Cnt) { \
1228
FDL_ASSERT(!((tex6Cnt) & ~((1 << CP_VAT_REG_C_TEX6CNT_SIZE)-1))); \
1229
cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX6CNT_MASK) | (((unsigned long)(tex6Cnt)) << CP_VAT_REG_C_TEX6CNT_SHIFT);\
1230
}
1231
#define CP_VAT_REG_C_TEX6FMT_SIZE 3
1232
#define CP_VAT_REG_C_TEX6FMT_SHIFT 15
1233
#define CP_VAT_REG_C_TEX6FMT_MASK 0x00038000
1234
#define CP_VAT_REG_C_GET_TEX6FMT(cp_vat_reg_c) \
1235
((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX6FMT_MASK) >> CP_VAT_REG_C_TEX6FMT_SHIFT)
1236
#define CP_VAT_REG_C_SET_TEX6FMT(cp_vat_reg_c, tex6Fmt) { \
1237
FDL_ASSERT(!((tex6Fmt) & ~((1 << CP_VAT_REG_C_TEX6FMT_SIZE)-1))); \
1238
cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX6FMT_MASK) | (((unsigned long)(tex6Fmt)) << CP_VAT_REG_C_TEX6FMT_SHIFT);\
1239
}
1240
#define CP_VAT_REG_C_TEX6SHFT_SIZE 5
1241
#define CP_VAT_REG_C_TEX6SHFT_SHIFT 18
1242
#define CP_VAT_REG_C_TEX6SHFT_MASK 0x007c0000
1243
#define CP_VAT_REG_C_GET_TEX6SHFT(cp_vat_reg_c) \
1244
((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX6SHFT_MASK) >> CP_VAT_REG_C_TEX6SHFT_SHIFT)
1245
#define CP_VAT_REG_C_SET_TEX6SHFT(cp_vat_reg_c, tex6Shft) { \
1246
FDL_ASSERT(!((tex6Shft) & ~((1 << CP_VAT_REG_C_TEX6SHFT_SIZE)-1))); \
1247
cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX6SHFT_MASK) | (((unsigned long)(tex6Shft)) << CP_VAT_REG_C_TEX6SHFT_SHIFT);\
1248
}
1249
#define CP_VAT_REG_C_TEX7CNT_SIZE 1
1250
#define CP_VAT_REG_C_TEX7CNT_SHIFT 23
1251
#define CP_VAT_REG_C_TEX7CNT_MASK 0x00800000
1252
#define CP_VAT_REG_C_GET_TEX7CNT(cp_vat_reg_c) \
1253
((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX7CNT_MASK) >> CP_VAT_REG_C_TEX7CNT_SHIFT)
1254
#define CP_VAT_REG_C_SET_TEX7CNT(cp_vat_reg_c, tex7Cnt) { \
1255
FDL_ASSERT(!((tex7Cnt) & ~((1 << CP_VAT_REG_C_TEX7CNT_SIZE)-1))); \
1256
cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX7CNT_MASK) | (((unsigned long)(tex7Cnt)) << CP_VAT_REG_C_TEX7CNT_SHIFT);\
1257
}
1258
#define CP_VAT_REG_C_TEX7FMT_SIZE 3
1259
#define CP_VAT_REG_C_TEX7FMT_SHIFT 24
1260
#define CP_VAT_REG_C_TEX7FMT_MASK 0x07000000
1261
#define CP_VAT_REG_C_GET_TEX7FMT(cp_vat_reg_c) \
1262
((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX7FMT_MASK) >> CP_VAT_REG_C_TEX7FMT_SHIFT)
1263
#define CP_VAT_REG_C_SET_TEX7FMT(cp_vat_reg_c, tex7Fmt) { \
1264
FDL_ASSERT(!((tex7Fmt) & ~((1 << CP_VAT_REG_C_TEX7FMT_SIZE)-1))); \
1265
cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX7FMT_MASK) | (((unsigned long)(tex7Fmt)) << CP_VAT_REG_C_TEX7FMT_SHIFT);\
1266
}
1267
#define CP_VAT_REG_C_TEX7SHFT_SIZE 5
1268
#define CP_VAT_REG_C_TEX7SHFT_SHIFT 27
1269
#define CP_VAT_REG_C_TEX7SHFT_MASK 0xf8000000
1270
#define CP_VAT_REG_C_GET_TEX7SHFT(cp_vat_reg_c) \
1271
((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX7SHFT_MASK) >> CP_VAT_REG_C_TEX7SHFT_SHIFT)
1272
#define CP_VAT_REG_C_SET_TEX7SHFT(cp_vat_reg_c, tex7Shft) { \
1273
FDL_ASSERT(!((tex7Shft) & ~((1 << CP_VAT_REG_C_TEX7SHFT_SIZE)-1))); \
1274
cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX7SHFT_MASK) | (((unsigned long)(tex7Shft)) << CP_VAT_REG_C_TEX7SHFT_SHIFT);\
1275
}
1276
#define CP_VAT_REG_C_TOTAL_SIZE 32
1277
#define CP_VAT_REG_C(tex4Shft, tex5Cnt, tex5Fmt, tex5Shft, tex6Cnt, tex6Fmt, tex6Shft, tex7Cnt, tex7Fmt, tex7Shft) \
1278
((((unsigned long)(tex4Shft)) << CP_VAT_REG_C_TEX4SHFT_SHIFT) | \
1279
(((unsigned long)(tex5Cnt)) << CP_VAT_REG_C_TEX5CNT_SHIFT) | \
1280
(((unsigned long)(tex5Fmt)) << CP_VAT_REG_C_TEX5FMT_SHIFT) | \
1281
(((unsigned long)(tex5Shft)) << CP_VAT_REG_C_TEX5SHFT_SHIFT) | \
1282
(((unsigned long)(tex6Cnt)) << CP_VAT_REG_C_TEX6CNT_SHIFT) | \
1283
(((unsigned long)(tex6Fmt)) << CP_VAT_REG_C_TEX6FMT_SHIFT) | \
1284
(((unsigned long)(tex6Shft)) << CP_VAT_REG_C_TEX6SHFT_SHIFT) | \
1285
(((unsigned long)(tex7Cnt)) << CP_VAT_REG_C_TEX7CNT_SHIFT) | \
1286
(((unsigned long)(tex7Fmt)) << CP_VAT_REG_C_TEX7FMT_SHIFT) | \
1287
(((unsigned long)(tex7Shft)) << CP_VAT_REG_C_TEX7SHFT_SHIFT))
1288
1289
/*
1290
* cp_matidx_reg_a struct
1291
*/
1292
#define CP_MATIDX_REG_A_POSIDX_SIZE 6
1293
#define CP_MATIDX_REG_A_POSIDX_SHIFT 0
1294
#define CP_MATIDX_REG_A_POSIDX_MASK 0x0000003f
1295
#define CP_MATIDX_REG_A_GET_POSIDX(cp_matidx_reg_a) \
1296
((((unsigned long)(cp_matidx_reg_a)) & CP_MATIDX_REG_A_POSIDX_MASK) >> CP_MATIDX_REG_A_POSIDX_SHIFT)
1297
#define CP_MATIDX_REG_A_SET_POSIDX(cp_matidx_reg_a, posIdx) { \
1298
FDL_ASSERT(!((posIdx) & ~((1 << CP_MATIDX_REG_A_POSIDX_SIZE)-1))); \
1299
cp_matidx_reg_a = (((unsigned long)(cp_matidx_reg_a)) & ~CP_MATIDX_REG_A_POSIDX_MASK) | (((unsigned long)(posIdx)) << CP_MATIDX_REG_A_POSIDX_SHIFT);\
1300
}
1301
#define CP_MATIDX_REG_A_TEX0IDX_SIZE 6
1302
#define CP_MATIDX_REG_A_TEX0IDX_SHIFT 6
1303
#define CP_MATIDX_REG_A_TEX0IDX_MASK 0x00000fc0
1304
#define CP_MATIDX_REG_A_GET_TEX0IDX(cp_matidx_reg_a) \
1305
((((unsigned long)(cp_matidx_reg_a)) & CP_MATIDX_REG_A_TEX0IDX_MASK) >> CP_MATIDX_REG_A_TEX0IDX_SHIFT)
1306
#define CP_MATIDX_REG_A_SET_TEX0IDX(cp_matidx_reg_a, tex0Idx) { \
1307
FDL_ASSERT(!((tex0Idx) & ~((1 << CP_MATIDX_REG_A_TEX0IDX_SIZE)-1))); \
1308
cp_matidx_reg_a = (((unsigned long)(cp_matidx_reg_a)) & ~CP_MATIDX_REG_A_TEX0IDX_MASK) | (((unsigned long)(tex0Idx)) << CP_MATIDX_REG_A_TEX0IDX_SHIFT);\
1309
}
1310
#define CP_MATIDX_REG_A_TEX1IDX_SIZE 6
1311
#define CP_MATIDX_REG_A_TEX1IDX_SHIFT 12
1312
#define CP_MATIDX_REG_A_TEX1IDX_MASK 0x0003f000
1313
#define CP_MATIDX_REG_A_GET_TEX1IDX(cp_matidx_reg_a) \
1314
((((unsigned long)(cp_matidx_reg_a)) & CP_MATIDX_REG_A_TEX1IDX_MASK) >> CP_MATIDX_REG_A_TEX1IDX_SHIFT)
1315
#define CP_MATIDX_REG_A_SET_TEX1IDX(cp_matidx_reg_a, tex1Idx) { \
1316
FDL_ASSERT(!((tex1Idx) & ~((1 << CP_MATIDX_REG_A_TEX1IDX_SIZE)-1))); \
1317
cp_matidx_reg_a = (((unsigned long)(cp_matidx_reg_a)) & ~CP_MATIDX_REG_A_TEX1IDX_MASK) | (((unsigned long)(tex1Idx)) << CP_MATIDX_REG_A_TEX1IDX_SHIFT);\
1318
}
1319
#define CP_MATIDX_REG_A_TEX2IDX_SIZE 6
1320
#define CP_MATIDX_REG_A_TEX2IDX_SHIFT 18
1321
#define CP_MATIDX_REG_A_TEX2IDX_MASK 0x00fc0000
1322
#define CP_MATIDX_REG_A_GET_TEX2IDX(cp_matidx_reg_a) \
1323
((((unsigned long)(cp_matidx_reg_a)) & CP_MATIDX_REG_A_TEX2IDX_MASK) >> CP_MATIDX_REG_A_TEX2IDX_SHIFT)
1324
#define CP_MATIDX_REG_A_SET_TEX2IDX(cp_matidx_reg_a, tex2Idx) { \
1325
FDL_ASSERT(!((tex2Idx) & ~((1 << CP_MATIDX_REG_A_TEX2IDX_SIZE)-1))); \
1326
cp_matidx_reg_a = (((unsigned long)(cp_matidx_reg_a)) & ~CP_MATIDX_REG_A_TEX2IDX_MASK) | (((unsigned long)(tex2Idx)) << CP_MATIDX_REG_A_TEX2IDX_SHIFT);\
1327
}
1328
#define CP_MATIDX_REG_A_TEX3IDX_SIZE 6
1329
#define CP_MATIDX_REG_A_TEX3IDX_SHIFT 24
1330
#define CP_MATIDX_REG_A_TEX3IDX_MASK 0x3f000000
1331
#define CP_MATIDX_REG_A_GET_TEX3IDX(cp_matidx_reg_a) \
1332
((((unsigned long)(cp_matidx_reg_a)) & CP_MATIDX_REG_A_TEX3IDX_MASK) >> CP_MATIDX_REG_A_TEX3IDX_SHIFT)
1333
#define CP_MATIDX_REG_A_SET_TEX3IDX(cp_matidx_reg_a, tex3Idx) { \
1334
FDL_ASSERT(!((tex3Idx) & ~((1 << CP_MATIDX_REG_A_TEX3IDX_SIZE)-1))); \
1335
cp_matidx_reg_a = (((unsigned long)(cp_matidx_reg_a)) & ~CP_MATIDX_REG_A_TEX3IDX_MASK) | (((unsigned long)(tex3Idx)) << CP_MATIDX_REG_A_TEX3IDX_SHIFT);\
1336
}
1337
#define CP_MATIDX_REG_A_TOTAL_SIZE 30
1338
#define CP_MATIDX_REG_A(posIdx, tex0Idx, tex1Idx, tex2Idx, tex3Idx) \
1339
((((unsigned long)(posIdx)) << CP_MATIDX_REG_A_POSIDX_SHIFT) | \
1340
(((unsigned long)(tex0Idx)) << CP_MATIDX_REG_A_TEX0IDX_SHIFT) | \
1341
(((unsigned long)(tex1Idx)) << CP_MATIDX_REG_A_TEX1IDX_SHIFT) | \
1342
(((unsigned long)(tex2Idx)) << CP_MATIDX_REG_A_TEX2IDX_SHIFT) | \
1343
(((unsigned long)(tex3Idx)) << CP_MATIDX_REG_A_TEX3IDX_SHIFT))
1344
1345
/*
1346
* cp_matidx_reg_b struct
1347
*/
1348
#define CP_MATIDX_REG_B_TEX4IDX_SIZE 6
1349
#define CP_MATIDX_REG_B_TEX4IDX_SHIFT 0
1350
#define CP_MATIDX_REG_B_TEX4IDX_MASK 0x0000003f
1351
#define CP_MATIDX_REG_B_GET_TEX4IDX(cp_matidx_reg_b) \
1352
((((unsigned long)(cp_matidx_reg_b)) & CP_MATIDX_REG_B_TEX4IDX_MASK) >> CP_MATIDX_REG_B_TEX4IDX_SHIFT)
1353
#define CP_MATIDX_REG_B_SET_TEX4IDX(cp_matidx_reg_b, tex4Idx) { \
1354
FDL_ASSERT(!((tex4Idx) & ~((1 << CP_MATIDX_REG_B_TEX4IDX_SIZE)-1))); \
1355
cp_matidx_reg_b = (((unsigned long)(cp_matidx_reg_b)) & ~CP_MATIDX_REG_B_TEX4IDX_MASK) | (((unsigned long)(tex4Idx)) << CP_MATIDX_REG_B_TEX4IDX_SHIFT);\
1356
}
1357
#define CP_MATIDX_REG_B_TEX5IDX_SIZE 6
1358
#define CP_MATIDX_REG_B_TEX5IDX_SHIFT 6
1359
#define CP_MATIDX_REG_B_TEX5IDX_MASK 0x00000fc0
1360
#define CP_MATIDX_REG_B_GET_TEX5IDX(cp_matidx_reg_b) \
1361
((((unsigned long)(cp_matidx_reg_b)) & CP_MATIDX_REG_B_TEX5IDX_MASK) >> CP_MATIDX_REG_B_TEX5IDX_SHIFT)
1362
#define CP_MATIDX_REG_B_SET_TEX5IDX(cp_matidx_reg_b, tex5Idx) { \
1363
FDL_ASSERT(!((tex5Idx) & ~((1 << CP_MATIDX_REG_B_TEX5IDX_SIZE)-1))); \
1364
cp_matidx_reg_b = (((unsigned long)(cp_matidx_reg_b)) & ~CP_MATIDX_REG_B_TEX5IDX_MASK) | (((unsigned long)(tex5Idx)) << CP_MATIDX_REG_B_TEX5IDX_SHIFT);\
1365
}
1366
#define CP_MATIDX_REG_B_TEX6IDX_SIZE 6
1367
#define CP_MATIDX_REG_B_TEX6IDX_SHIFT 12
1368
#define CP_MATIDX_REG_B_TEX6IDX_MASK 0x0003f000
1369
#define CP_MATIDX_REG_B_GET_TEX6IDX(cp_matidx_reg_b) \
1370
((((unsigned long)(cp_matidx_reg_b)) & CP_MATIDX_REG_B_TEX6IDX_MASK) >> CP_MATIDX_REG_B_TEX6IDX_SHIFT)
1371
#define CP_MATIDX_REG_B_SET_TEX6IDX(cp_matidx_reg_b, tex6Idx) { \
1372
FDL_ASSERT(!((tex6Idx) & ~((1 << CP_MATIDX_REG_B_TEX6IDX_SIZE)-1))); \
1373
cp_matidx_reg_b = (((unsigned long)(cp_matidx_reg_b)) & ~CP_MATIDX_REG_B_TEX6IDX_MASK) | (((unsigned long)(tex6Idx)) << CP_MATIDX_REG_B_TEX6IDX_SHIFT);\
1374
}
1375
#define CP_MATIDX_REG_B_TEX7IDX_SIZE 6
1376
#define CP_MATIDX_REG_B_TEX7IDX_SHIFT 18
1377
#define CP_MATIDX_REG_B_TEX7IDX_MASK 0x00fc0000
1378
#define CP_MATIDX_REG_B_GET_TEX7IDX(cp_matidx_reg_b) \
1379
((((unsigned long)(cp_matidx_reg_b)) & CP_MATIDX_REG_B_TEX7IDX_MASK) >> CP_MATIDX_REG_B_TEX7IDX_SHIFT)
1380
#define CP_MATIDX_REG_B_SET_TEX7IDX(cp_matidx_reg_b, tex7Idx) { \
1381
FDL_ASSERT(!((tex7Idx) & ~((1 << CP_MATIDX_REG_B_TEX7IDX_SIZE)-1))); \
1382
cp_matidx_reg_b = (((unsigned long)(cp_matidx_reg_b)) & ~CP_MATIDX_REG_B_TEX7IDX_MASK) | (((unsigned long)(tex7Idx)) << CP_MATIDX_REG_B_TEX7IDX_SHIFT);\
1383
}
1384
#define CP_MATIDX_REG_B_TOTAL_SIZE 24
1385
#define CP_MATIDX_REG_B(tex4Idx, tex5Idx, tex6Idx, tex7Idx) \
1386
((((unsigned long)(tex4Idx)) << CP_MATIDX_REG_B_TEX4IDX_SHIFT) | \
1387
(((unsigned long)(tex5Idx)) << CP_MATIDX_REG_B_TEX5IDX_SHIFT) | \
1388
(((unsigned long)(tex6Idx)) << CP_MATIDX_REG_B_TEX6IDX_SHIFT) | \
1389
(((unsigned long)(tex7Idx)) << CP_MATIDX_REG_B_TEX7IDX_SHIFT))
1390
1391
/*
1392
* cp_array_base_reg struct
1393
*/
1394
#define CP_ARRAY_BASE_REG_BASE_SIZE 29
1395
#define CP_ARRAY_BASE_REG_BASE_SHIFT 0
1396
#define CP_ARRAY_BASE_REG_BASE_MASK 0x1fffffff
1397
#define CP_ARRAY_BASE_REG_GET_BASE(cp_array_base_reg) \
1398
((((unsigned long)(cp_array_base_reg)) & CP_ARRAY_BASE_REG_BASE_MASK) >> CP_ARRAY_BASE_REG_BASE_SHIFT)
1399
#define CP_ARRAY_BASE_REG_SET_BASE(cp_array_base_reg, base) { \
1400
FDL_ASSERT(!((base) & ~((1 << CP_ARRAY_BASE_REG_BASE_SIZE)-1))); \
1401
cp_array_base_reg = (((unsigned long)(cp_array_base_reg)) & ~CP_ARRAY_BASE_REG_BASE_MASK) | (((unsigned long)(base)) << CP_ARRAY_BASE_REG_BASE_SHIFT);\
1402
}
1403
#define CP_ARRAY_BASE_REG_PAD0_SIZE 3
1404
#define CP_ARRAY_BASE_REG_PAD0_SHIFT 29
1405
#define CP_ARRAY_BASE_REG_PAD0_MASK 0xe0000000
1406
#define CP_ARRAY_BASE_REG_GET_PAD0(cp_array_base_reg) \
1407
((((unsigned long)(cp_array_base_reg)) & CP_ARRAY_BASE_REG_PAD0_MASK) >> CP_ARRAY_BASE_REG_PAD0_SHIFT)
1408
#define CP_ARRAY_BASE_REG_SET_PAD0(cp_array_base_reg, pad0) { \
1409
FDL_ASSERT(!((pad0) & ~((1 << CP_ARRAY_BASE_REG_PAD0_SIZE)-1))); \
1410
cp_array_base_reg = (((unsigned long)(cp_array_base_reg)) & ~CP_ARRAY_BASE_REG_PAD0_MASK) | (((unsigned long)(pad0)) << CP_ARRAY_BASE_REG_PAD0_SHIFT);\
1411
}
1412
#define CP_ARRAY_BASE_REG_TOTAL_SIZE 32
1413
#define CP_ARRAY_BASE_REG(base) \
1414
((((unsigned long)(base)) << CP_ARRAY_BASE_REG_BASE_SHIFT))
1415
1416
/*
1417
* cp_array_stride_reg struct
1418
*/
1419
#define CP_ARRAY_STRIDE_REG_STRIDE_SIZE 8
1420
#define CP_ARRAY_STRIDE_REG_STRIDE_SHIFT 0
1421
#define CP_ARRAY_STRIDE_REG_STRIDE_MASK 0x000000ff
1422
#define CP_ARRAY_STRIDE_REG_GET_STRIDE(cp_array_stride_reg) \
1423
((((unsigned long)(cp_array_stride_reg)) & CP_ARRAY_STRIDE_REG_STRIDE_MASK) >> CP_ARRAY_STRIDE_REG_STRIDE_SHIFT)
1424
#define CP_ARRAY_STRIDE_REG_SET_STRIDE(cp_array_stride_reg, stride) { \
1425
FDL_ASSERT(!((stride) & ~((1 << CP_ARRAY_STRIDE_REG_STRIDE_SIZE)-1))); \
1426
cp_array_stride_reg = (((unsigned long)(cp_array_stride_reg)) & ~CP_ARRAY_STRIDE_REG_STRIDE_MASK) | (((unsigned long)(stride)) << CP_ARRAY_STRIDE_REG_STRIDE_SHIFT);\
1427
}
1428
#define CP_ARRAY_STRIDE_REG_PAD0_SIZE 24
1429
#define CP_ARRAY_STRIDE_REG_PAD0_SHIFT 8
1430
#define CP_ARRAY_STRIDE_REG_PAD0_MASK 0xffffff00
1431
#define CP_ARRAY_STRIDE_REG_GET_PAD0(cp_array_stride_reg) \
1432
((((unsigned long)(cp_array_stride_reg)) & CP_ARRAY_STRIDE_REG_PAD0_MASK) >> CP_ARRAY_STRIDE_REG_PAD0_SHIFT)
1433
#define CP_ARRAY_STRIDE_REG_SET_PAD0(cp_array_stride_reg, pad0) { \
1434
FDL_ASSERT(!((pad0) & ~((1 << CP_ARRAY_STRIDE_REG_PAD0_SIZE)-1))); \
1435
cp_array_stride_reg = (((unsigned long)(cp_array_stride_reg)) & ~CP_ARRAY_STRIDE_REG_PAD0_MASK) | (((unsigned long)(pad0)) << CP_ARRAY_STRIDE_REG_PAD0_SHIFT);\
1436
}
1437
#define CP_ARRAY_STRIDE_REG_TOTAL_SIZE 32
1438
#define CP_ARRAY_STRIDE_REG(stride) \
1439
((((unsigned long)(stride)) << CP_ARRAY_STRIDE_REG_STRIDE_SHIFT))
1440
1441
/*
1442
* cp_stat_enable_reg struct
1443
*/
1444
#define CP_STAT_ENABLE_REG_VC_STAT_SIZE 1
1445
#define CP_STAT_ENABLE_REG_VC_STAT_SHIFT 0
1446
#define CP_STAT_ENABLE_REG_VC_STAT_MASK 0x00000001
1447
#define CP_STAT_ENABLE_REG_GET_VC_STAT(cp_stat_enable_reg) \
1448
((((unsigned long)(cp_stat_enable_reg)) & CP_STAT_ENABLE_REG_VC_STAT_MASK) >> CP_STAT_ENABLE_REG_VC_STAT_SHIFT)
1449
#define CP_STAT_ENABLE_REG_SET_VC_STAT(cp_stat_enable_reg, vc_stat) { \
1450
FDL_ASSERT(!((vc_stat) & ~((1 << CP_STAT_ENABLE_REG_VC_STAT_SIZE)-1))); \
1451
cp_stat_enable_reg = (((unsigned long)(cp_stat_enable_reg)) & ~CP_STAT_ENABLE_REG_VC_STAT_MASK) | (((unsigned long)(vc_stat)) << CP_STAT_ENABLE_REG_VC_STAT_SHIFT);\
1452
}
1453
#define CP_STAT_ENABLE_REG_PAD0_SIZE 1
1454
#define CP_STAT_ENABLE_REG_PAD0_SHIFT 1
1455
#define CP_STAT_ENABLE_REG_PAD0_MASK 0x00000002
1456
#define CP_STAT_ENABLE_REG_GET_PAD0(cp_stat_enable_reg) \
1457
((((unsigned long)(cp_stat_enable_reg)) & CP_STAT_ENABLE_REG_PAD0_MASK) >> CP_STAT_ENABLE_REG_PAD0_SHIFT)
1458
#define CP_STAT_ENABLE_REG_SET_PAD0(cp_stat_enable_reg, pad0) { \
1459
FDL_ASSERT(!((pad0) & ~((1 << CP_STAT_ENABLE_REG_PAD0_SIZE)-1))); \
1460
cp_stat_enable_reg = (((unsigned long)(cp_stat_enable_reg)) & ~CP_STAT_ENABLE_REG_PAD0_MASK) | (((unsigned long)(pad0)) << CP_STAT_ENABLE_REG_PAD0_SHIFT);\
1461
}
1462
#define CP_STAT_ENABLE_REG_FRCLK_SIZE 1
1463
#define CP_STAT_ENABLE_REG_FRCLK_SHIFT 2
1464
#define CP_STAT_ENABLE_REG_FRCLK_MASK 0x00000004
1465
#define CP_STAT_ENABLE_REG_GET_FRCLK(cp_stat_enable_reg) \
1466
((((unsigned long)(cp_stat_enable_reg)) & CP_STAT_ENABLE_REG_FRCLK_MASK) >> CP_STAT_ENABLE_REG_FRCLK_SHIFT)
1467
#define CP_STAT_ENABLE_REG_SET_FRCLK(cp_stat_enable_reg, frclk) { \
1468
FDL_ASSERT(!((frclk) & ~((1 << CP_STAT_ENABLE_REG_FRCLK_SIZE)-1))); \
1469
cp_stat_enable_reg = (((unsigned long)(cp_stat_enable_reg)) & ~CP_STAT_ENABLE_REG_FRCLK_MASK) | (((unsigned long)(frclk)) << CP_STAT_ENABLE_REG_FRCLK_SHIFT);\
1470
}
1471
#define CP_STAT_ENABLE_REG_TOTAL_SIZE 3
1472
#define CP_STAT_ENABLE_REG(vc_stat, frclk) \
1473
((((unsigned long)(vc_stat)) << CP_STAT_ENABLE_REG_VC_STAT_SHIFT) | \
1474
(((unsigned long)(frclk)) << CP_STAT_ENABLE_REG_FRCLK_SHIFT))
1475
1476
/*
1477
* cp_stat_sel_reg struct
1478
*/
1479
#define CP_STAT_SEL_REG_ATTR_SEL_SIZE 4
1480
#define CP_STAT_SEL_REG_ATTR_SEL_SHIFT 0
1481
#define CP_STAT_SEL_REG_ATTR_SEL_MASK 0x0000000f
1482
#define CP_STAT_SEL_REG_GET_ATTR_SEL(cp_stat_sel_reg) \
1483
((((unsigned long)(cp_stat_sel_reg)) & CP_STAT_SEL_REG_ATTR_SEL_MASK) >> CP_STAT_SEL_REG_ATTR_SEL_SHIFT)
1484
#define CP_STAT_SEL_REG_SET_ATTR_SEL(cp_stat_sel_reg, attr_sel) { \
1485
FDL_ASSERT(!((attr_sel) & ~((1 << CP_STAT_SEL_REG_ATTR_SEL_SIZE)-1))); \
1486
cp_stat_sel_reg = (((unsigned long)(cp_stat_sel_reg)) & ~CP_STAT_SEL_REG_ATTR_SEL_MASK) | (((unsigned long)(attr_sel)) << CP_STAT_SEL_REG_ATTR_SEL_SHIFT);\
1487
}
1488
#define CP_STAT_SEL_REG_STALLPERF_SEL_SIZE 4
1489
#define CP_STAT_SEL_REG_STALLPERF_SEL_SHIFT 4
1490
#define CP_STAT_SEL_REG_STALLPERF_SEL_MASK 0x000000f0
1491
#define CP_STAT_SEL_REG_GET_STALLPERF_SEL(cp_stat_sel_reg) \
1492
((((unsigned long)(cp_stat_sel_reg)) & CP_STAT_SEL_REG_STALLPERF_SEL_MASK) >> CP_STAT_SEL_REG_STALLPERF_SEL_SHIFT)
1493
#define CP_STAT_SEL_REG_SET_STALLPERF_SEL(cp_stat_sel_reg, stallperf_sel) { \
1494
FDL_ASSERT(!((stallperf_sel) & ~((1 << CP_STAT_SEL_REG_STALLPERF_SEL_SIZE)-1))); \
1495
cp_stat_sel_reg = (((unsigned long)(cp_stat_sel_reg)) & ~CP_STAT_SEL_REG_STALLPERF_SEL_MASK) | (((unsigned long)(stallperf_sel)) << CP_STAT_SEL_REG_STALLPERF_SEL_SHIFT);\
1496
}
1497
#define CP_STAT_SEL_REG_TOTAL_SIZE 8
1498
#define CP_STAT_SEL_REG(attr_sel, stallperf_sel) \
1499
((((unsigned long)(attr_sel)) << CP_STAT_SEL_REG_ATTR_SEL_SHIFT) | \
1500
(((unsigned long)(stallperf_sel)) << CP_STAT_SEL_REG_STALLPERF_SEL_SHIFT))
1501
1502
/*
1503
* cp_stallperf_sel enum
1504
*/
1505
#define STALLPERF_ZERO 0x00000000
1506
#define STALLPERF_ONE 0x00000001
1507
#define ELEMQ_FULL 0x00000002
1508
#define MISSQ_FULL 0x00000003
1509
#define MEMREQ_FULL 0x00000004
1510
#define VC_STATCNT7 0x00000005
1511
#define VC_MISS_REP_FULL 0x00000006
1512
#define VC_STALL_STMBUFLOW 0x00000007
1513
#define VTX_CNT 0x00000008
1514
#define ALL_STALL 0x00000009
1515
#define CP_STALLPERF_SEL_UNUSED_10 0x0000000a
1516
#define CP_STALLPERF_SEL_UNUSED_11 0x0000000b
1517
#define CP_STALLPERF_SEL_UNUSED_12 0x0000000c
1518
#define CP_STALLPERF_SEL_UNUSED_13 0x0000000d
1519
#define CP_STALLPERF_SEL_UNUSED_14 0x0000000e
1520
#define CP_STALLPERF_SEL_UNUSED_15 0x0000000f
1521
1522
/*
1523
* cp_array_addr value
1524
*/
1525
#define ATTR_ARRAY_POS 0x0
1526
#define ATTR_ARRAY_NRM 0x1
1527
#define ATTR_ARRAY_COL0 0x2
1528
#define ATTR_ARRAY_COL1 0x3
1529
#define ATTR_ARRAY_TEX0 0x4
1530
#define ATTR_ARRAY_TEX1 0x5
1531
#define ATTR_ARRAY_TEX2 0x6
1532
#define ATTR_ARRAY_TEX3 0x7
1533
#define ATTR_ARRAY_TEX4 0x8
1534
#define ATTR_ARRAY_TEX5 0x9
1535
#define ATTR_ARRAY_TEX6 0xa
1536
#define ATTR_ARRAY_TEX7 0xb
1537
#define ATTR_ARRAY_XFINDREGA 0xc
1538
#define ATTR_ARRAY_XFINDREGB 0xd
1539
#define ATTR_ARRAY_XFINDREGC 0xe
1540
#define ATTR_ARRAY_XFINDREGD 0xf
1541
1542
/*
1543
* cp_xf_loadregs struct
1544
*/
1545
#define CP_XF_LOADREGS_ADDR_SIZE 16
1546
#define CP_XF_LOADREGS_ADDR_SHIFT 0
1547
#define CP_XF_LOADREGS_ADDR_MASK 0x0000ffff
1548
#define CP_XF_LOADREGS_GET_ADDR(cp_xf_loadregs) \
1549
((((unsigned long)(cp_xf_loadregs)) & CP_XF_LOADREGS_ADDR_MASK) >> CP_XF_LOADREGS_ADDR_SHIFT)
1550
#define CP_XF_LOADREGS_SET_ADDR(cp_xf_loadregs, addr) { \
1551
FDL_ASSERT(!((addr) & ~((1 << CP_XF_LOADREGS_ADDR_SIZE)-1))); \
1552
cp_xf_loadregs = (((unsigned long)(cp_xf_loadregs)) & ~CP_XF_LOADREGS_ADDR_MASK) | (((unsigned long)(addr)) << CP_XF_LOADREGS_ADDR_SHIFT);\
1553
}
1554
#define CP_XF_LOADREGS_CNT_SIZE 4
1555
#define CP_XF_LOADREGS_CNT_SHIFT 16
1556
#define CP_XF_LOADREGS_CNT_MASK 0x000f0000
1557
#define CP_XF_LOADREGS_GET_CNT(cp_xf_loadregs) \
1558
((((unsigned long)(cp_xf_loadregs)) & CP_XF_LOADREGS_CNT_MASK) >> CP_XF_LOADREGS_CNT_SHIFT)
1559
#define CP_XF_LOADREGS_SET_CNT(cp_xf_loadregs, cnt) { \
1560
FDL_ASSERT(!((cnt) & ~((1 << CP_XF_LOADREGS_CNT_SIZE)-1))); \
1561
cp_xf_loadregs = (((unsigned long)(cp_xf_loadregs)) & ~CP_XF_LOADREGS_CNT_MASK) | (((unsigned long)(cnt)) << CP_XF_LOADREGS_CNT_SHIFT);\
1562
}
1563
#define CP_XF_LOADREGS_TOTAL_SIZE 20
1564
#define CP_XF_LOADREGS_UNUSED_SIZE 12
1565
1566
#define CP_XF_LOADREGS(addr, cnt) \
1567
((((unsigned long)(addr)) << CP_XF_LOADREGS_ADDR_SHIFT) | \
1568
(((unsigned long)(cnt)) << CP_XF_LOADREGS_CNT_SHIFT))
1569
1570
/*
1571
* cp_xf_loadindex struct
1572
*/
1573
#define CP_XF_LOADINDEX_ADDR_SIZE 12
1574
#define CP_XF_LOADINDEX_ADDR_SHIFT 0
1575
#define CP_XF_LOADINDEX_ADDR_MASK 0x00000fff
1576
#define CP_XF_LOADINDEX_GET_ADDR(cp_xf_loadindex) \
1577
((((unsigned long)(cp_xf_loadindex)) & CP_XF_LOADINDEX_ADDR_MASK) >> CP_XF_LOADINDEX_ADDR_SHIFT)
1578
#define CP_XF_LOADINDEX_SET_ADDR(cp_xf_loadindex, addr) { \
1579
FDL_ASSERT(!((addr) & ~((1 << CP_XF_LOADINDEX_ADDR_SIZE)-1))); \
1580
cp_xf_loadindex = (((unsigned long)(cp_xf_loadindex)) & ~CP_XF_LOADINDEX_ADDR_MASK) | (((unsigned long)(addr)) << CP_XF_LOADINDEX_ADDR_SHIFT);\
1581
}
1582
#define CP_XF_LOADINDEX_CNT_SIZE 4
1583
#define CP_XF_LOADINDEX_CNT_SHIFT 12
1584
#define CP_XF_LOADINDEX_CNT_MASK 0x0000f000
1585
#define CP_XF_LOADINDEX_GET_CNT(cp_xf_loadindex) \
1586
((((unsigned long)(cp_xf_loadindex)) & CP_XF_LOADINDEX_CNT_MASK) >> CP_XF_LOADINDEX_CNT_SHIFT)
1587
#define CP_XF_LOADINDEX_SET_CNT(cp_xf_loadindex, cnt) { \
1588
FDL_ASSERT(!((cnt) & ~((1 << CP_XF_LOADINDEX_CNT_SIZE)-1))); \
1589
cp_xf_loadindex = (((unsigned long)(cp_xf_loadindex)) & ~CP_XF_LOADINDEX_CNT_MASK) | (((unsigned long)(cnt)) << CP_XF_LOADINDEX_CNT_SHIFT);\
1590
}
1591
#define CP_XF_LOADINDEX_IDX_SIZE 16
1592
#define CP_XF_LOADINDEX_IDX_SHIFT 16
1593
#define CP_XF_LOADINDEX_IDX_MASK 0xffff0000
1594
#define CP_XF_LOADINDEX_GET_IDX(cp_xf_loadindex) \
1595
((((unsigned long)(cp_xf_loadindex)) & CP_XF_LOADINDEX_IDX_MASK) >> CP_XF_LOADINDEX_IDX_SHIFT)
1596
#define CP_XF_LOADINDEX_SET_IDX(cp_xf_loadindex, idx) { \
1597
FDL_ASSERT(!((idx) & ~((1 << CP_XF_LOADINDEX_IDX_SIZE)-1))); \
1598
cp_xf_loadindex = (((unsigned long)(cp_xf_loadindex)) & ~CP_XF_LOADINDEX_IDX_MASK) | (((unsigned long)(idx)) << CP_XF_LOADINDEX_IDX_SHIFT);\
1599
}
1600
#define CP_XF_LOADINDEX_TOTAL_SIZE 32
1601
#define CP_XF_LOADINDEX(addr, cnt, idx) \
1602
((((unsigned long)(addr)) << CP_XF_LOADINDEX_ADDR_SHIFT) | \
1603
(((unsigned long)(cnt)) << CP_XF_LOADINDEX_CNT_SHIFT) | \
1604
(((unsigned long)(idx)) << CP_XF_LOADINDEX_IDX_SHIFT))
1605
1606
/*
1607
* cp_callobj_d1 struct
1608
*/
1609
#define CP_CALLOBJ_D1_PAD0_SIZE 5
1610
#define CP_CALLOBJ_D1_PAD0_SHIFT 0
1611
#define CP_CALLOBJ_D1_PAD0_MASK 0x0000001f
1612
#define CP_CALLOBJ_D1_GET_PAD0(cp_callobj_d1) \
1613
((((unsigned long)(cp_callobj_d1)) & CP_CALLOBJ_D1_PAD0_MASK) >> CP_CALLOBJ_D1_PAD0_SHIFT)
1614
#define CP_CALLOBJ_D1_SET_PAD0(cp_callobj_d1, pad0) { \
1615
FDL_ASSERT(!((pad0) & ~((1 << CP_CALLOBJ_D1_PAD0_SIZE)-1))); \
1616
cp_callobj_d1 = (((unsigned long)(cp_callobj_d1)) & ~CP_CALLOBJ_D1_PAD0_MASK) | (((unsigned long)(pad0)) << CP_CALLOBJ_D1_PAD0_SHIFT);\
1617
}
1618
#define CP_CALLOBJ_D1_ADDR_SIZE 24
1619
#define CP_CALLOBJ_D1_ADDR_SHIFT 5
1620
#define CP_CALLOBJ_D1_ADDR_MASK 0x1fffffe0
1621
#define CP_CALLOBJ_D1_GET_ADDR(cp_callobj_d1) \
1622
((((unsigned long)(cp_callobj_d1)) & CP_CALLOBJ_D1_ADDR_MASK) >> CP_CALLOBJ_D1_ADDR_SHIFT)
1623
#define CP_CALLOBJ_D1_SET_ADDR(cp_callobj_d1, addr) { \
1624
FDL_ASSERT(!((addr) & ~((1 << CP_CALLOBJ_D1_ADDR_SIZE)-1))); \
1625
cp_callobj_d1 = (((unsigned long)(cp_callobj_d1)) & ~CP_CALLOBJ_D1_ADDR_MASK) | (((unsigned long)(addr)) << CP_CALLOBJ_D1_ADDR_SHIFT);\
1626
}
1627
#define CP_CALLOBJ_D1_TOTAL_SIZE 29
1628
#define CP_CALLOBJ_D1_UNUSED_SIZE 3
1629
1630
#define CP_CALLOBJ_D1(addr) \
1631
((((unsigned long)(addr)) << CP_CALLOBJ_D1_ADDR_SHIFT))
1632
1633
/*
1634
* cp_callobj_d2 struct
1635
*/
1636
#define CP_CALLOBJ_D2_PAD0_SIZE 5
1637
#define CP_CALLOBJ_D2_PAD0_SHIFT 0
1638
#define CP_CALLOBJ_D2_PAD0_MASK 0x0000001f
1639
#define CP_CALLOBJ_D2_GET_PAD0(cp_callobj_d2) \
1640
((((unsigned long)(cp_callobj_d2)) & CP_CALLOBJ_D2_PAD0_MASK) >> CP_CALLOBJ_D2_PAD0_SHIFT)
1641
#define CP_CALLOBJ_D2_SET_PAD0(cp_callobj_d2, pad0) { \
1642
FDL_ASSERT(!((pad0) & ~((1 << CP_CALLOBJ_D2_PAD0_SIZE)-1))); \
1643
cp_callobj_d2 = (((unsigned long)(cp_callobj_d2)) & ~CP_CALLOBJ_D2_PAD0_MASK) | (((unsigned long)(pad0)) << CP_CALLOBJ_D2_PAD0_SHIFT);\
1644
}
1645
#define CP_CALLOBJ_D2_CNT_SIZE 24
1646
#define CP_CALLOBJ_D2_CNT_SHIFT 5
1647
#define CP_CALLOBJ_D2_CNT_MASK 0x1fffffe0
1648
#define CP_CALLOBJ_D2_GET_CNT(cp_callobj_d2) \
1649
((((unsigned long)(cp_callobj_d2)) & CP_CALLOBJ_D2_CNT_MASK) >> CP_CALLOBJ_D2_CNT_SHIFT)
1650
#define CP_CALLOBJ_D2_SET_CNT(cp_callobj_d2, cnt) { \
1651
FDL_ASSERT(!((cnt) & ~((1 << CP_CALLOBJ_D2_CNT_SIZE)-1))); \
1652
cp_callobj_d2 = (((unsigned long)(cp_callobj_d2)) & ~CP_CALLOBJ_D2_CNT_MASK) | (((unsigned long)(cnt)) << CP_CALLOBJ_D2_CNT_SHIFT);\
1653
}
1654
#define CP_CALLOBJ_D2_TOTAL_SIZE 29
1655
#define CP_CALLOBJ_D2_UNUSED_SIZE 3
1656
1657
#define CP_CALLOBJ_D2(cnt) \
1658
((((unsigned long)(cnt)) << CP_CALLOBJ_D2_CNT_SHIFT))
1659
1660
1661
1662
#define SC_CP_OPCODE_SET_INDEX(line, cp_opcode,index) \
1663
FAST_GPFLAGSET(line, cp_opcode,index,CP_OPCODE_INDEX)
1664
1665
#define SC_CP_OPCODE_SET_CMD(line, cp_opcode,cmd) \
1666
FAST_GPFLAGSET(line, cp_opcode,cmd,CP_OPCODE_CMD)
1667
1668
#define SC_CP_STREAM_REG_SET_INDEX(line, cp_stream_reg,index) \
1669
FAST_GPFLAGSET(line, cp_stream_reg,index,CP_STREAM_REG_INDEX)
1670
1671
#define SC_CP_STREAM_REG_SET_ADDR(line, cp_stream_reg,addr) \
1672
FAST_GPFLAGSET(line, cp_stream_reg,addr,CP_STREAM_REG_ADDR)
1673
1674
#define SC_CP_REG_STATUS_SET_OVFL(line, cp_reg_status,ovfl) \
1675
FAST_GPFLAGSET(line, cp_reg_status,ovfl,CP_REG_STATUS_OVFL)
1676
1677
#define SC_CP_REG_STATUS_SET_UNFL(line, cp_reg_status,unfl) \
1678
FAST_GPFLAGSET(line, cp_reg_status,unfl,CP_REG_STATUS_UNFL)
1679
1680
#define SC_CP_REG_STATUS_SET_FIFO_RDIDLE(line, cp_reg_status,fifo_rdidle) \
1681
FAST_GPFLAGSET(line, cp_reg_status,fifo_rdidle,CP_REG_STATUS_FIFO_RDIDLE)
1682
1683
#define SC_CP_REG_STATUS_SET_CPIDLE(line, cp_reg_status,cpidle) \
1684
FAST_GPFLAGSET(line, cp_reg_status,cpidle,CP_REG_STATUS_CPIDLE)
1685
1686
#define SC_CP_REG_STATUS_SET_FIFOBRK(line, cp_reg_status,fifobrk) \
1687
FAST_GPFLAGSET(line, cp_reg_status,fifobrk,CP_REG_STATUS_FIFOBRK)
1688
1689
#define SC_CP_REG_ENABLE_SET_FIFORD(line, cp_reg_enable,fiford) \
1690
FAST_GPFLAGSET(line, cp_reg_enable,fiford,CP_REG_ENABLE_FIFORD)
1691
1692
#define SC_CP_REG_ENABLE_SET_FIFOBRK(line, cp_reg_enable,fifobrk) \
1693
FAST_GPFLAGSET(line, cp_reg_enable,fifobrk,CP_REG_ENABLE_FIFOBRK)
1694
1695
#define SC_CP_REG_ENABLE_SET_OVFLINT(line, cp_reg_enable,ovflint) \
1696
FAST_GPFLAGSET(line, cp_reg_enable,ovflint,CP_REG_ENABLE_OVFLINT)
1697
1698
#define SC_CP_REG_ENABLE_SET_UNFLINT(line, cp_reg_enable,unflint) \
1699
FAST_GPFLAGSET(line, cp_reg_enable,unflint,CP_REG_ENABLE_UNFLINT)
1700
1701
#define SC_CP_REG_ENABLE_SET_WRPTRINC(line, cp_reg_enable,wrptrinc) \
1702
FAST_GPFLAGSET(line, cp_reg_enable,wrptrinc,CP_REG_ENABLE_WRPTRINC)
1703
1704
#define SC_CP_REG_ENABLE_SET_FIFOBRKINT(line, cp_reg_enable,fifobrkint) \
1705
FAST_GPFLAGSET(line, cp_reg_enable,fifobrkint,CP_REG_ENABLE_FIFOBRKINT)
1706
1707
#define SC_CP_REG_CLR_SET_OVFLINT(line, cp_reg_clr,ovflint) \
1708
FAST_GPFLAGSET(line, cp_reg_clr,ovflint,CP_REG_CLR_OVFLINT)
1709
1710
#define SC_CP_REG_CLR_SET_UNFLINT(line, cp_reg_clr,unflint) \
1711
FAST_GPFLAGSET(line, cp_reg_clr,unflint,CP_REG_CLR_UNFLINT)
1712
1713
#define SC_CP_REG_CLR_SET_PERFCNT(line, cp_reg_clr,perfcnt) \
1714
FAST_GPFLAGSET(line, cp_reg_clr,perfcnt,CP_REG_CLR_PERFCNT)
1715
1716
#define SC_CP_REG_MEMPERFSEL_SET_PERFSEL(line, cp_reg_memperfsel,perfsel) \
1717
FAST_GPFLAGSET(line, cp_reg_memperfsel,perfsel,CP_REG_MEMPERFSEL_PERFSEL)
1718
1719
#define SC_CP_REG_FIFO_BASEL_SET_PAD0(line, cp_reg_fifo_basel,pad0) \
1720
FAST_GPFLAGSET(line, cp_reg_fifo_basel,pad0,CP_REG_FIFO_BASEL_PAD0)
1721
1722
#define SC_CP_REG_FIFO_BASEL_SET_ADDR(line, cp_reg_fifo_basel,addr) \
1723
FAST_GPFLAGSET(line, cp_reg_fifo_basel,addr,CP_REG_FIFO_BASEL_ADDR)
1724
1725
#define SC_CP_REG_FIFO_BASEH_SET_ADDR(line, cp_reg_fifo_baseh,addr) \
1726
FAST_GPFLAGSET(line, cp_reg_fifo_baseh,addr,CP_REG_FIFO_BASEH_ADDR)
1727
1728
#define SC_CP_REG_FIFO_TOPL_SET_PAD0(line, cp_reg_fifo_topl,pad0) \
1729
FAST_GPFLAGSET(line, cp_reg_fifo_topl,pad0,CP_REG_FIFO_TOPL_PAD0)
1730
1731
#define SC_CP_REG_FIFO_TOPL_SET_ADDR(line, cp_reg_fifo_topl,addr) \
1732
FAST_GPFLAGSET(line, cp_reg_fifo_topl,addr,CP_REG_FIFO_TOPL_ADDR)
1733
1734
#define SC_CP_REG_FIFO_TOPH_SET_ADDR(line, cp_reg_fifo_toph,addr) \
1735
FAST_GPFLAGSET(line, cp_reg_fifo_toph,addr,CP_REG_FIFO_TOPH_ADDR)
1736
1737
#define SC_CP_REG_FIFO_HICNTL_SET_PAD0(line, cp_reg_fifo_hicntl,pad0) \
1738
FAST_GPFLAGSET(line, cp_reg_fifo_hicntl,pad0,CP_REG_FIFO_HICNTL_PAD0)
1739
1740
#define SC_CP_REG_FIFO_HICNTL_SET_ADDR(line, cp_reg_fifo_hicntl,addr) \
1741
FAST_GPFLAGSET(line, cp_reg_fifo_hicntl,addr,CP_REG_FIFO_HICNTL_ADDR)
1742
1743
#define SC_CP_REG_FIFO_HICNTH_SET_ADDR(line, cp_reg_fifo_hicnth,addr) \
1744
FAST_GPFLAGSET(line, cp_reg_fifo_hicnth,addr,CP_REG_FIFO_HICNTH_ADDR)
1745
1746
#define SC_CP_REG_FIFO_LOCNTL_SET_PAD0(line, cp_reg_fifo_locntl,pad0) \
1747
FAST_GPFLAGSET(line, cp_reg_fifo_locntl,pad0,CP_REG_FIFO_LOCNTL_PAD0)
1748
1749
#define SC_CP_REG_FIFO_LOCNTL_SET_ADDR(line, cp_reg_fifo_locntl,addr) \
1750
FAST_GPFLAGSET(line, cp_reg_fifo_locntl,addr,CP_REG_FIFO_LOCNTL_ADDR)
1751
1752
#define SC_CP_REG_FIFO_LOCNTH_SET_ADDR(line, cp_reg_fifo_locnth,addr) \
1753
FAST_GPFLAGSET(line, cp_reg_fifo_locnth,addr,CP_REG_FIFO_LOCNTH_ADDR)
1754
1755
#define SC_CP_REG_FIFO_COUNTL_SET_PAD0(line, cp_reg_fifo_countl,pad0) \
1756
FAST_GPFLAGSET(line, cp_reg_fifo_countl,pad0,CP_REG_FIFO_COUNTL_PAD0)
1757
1758
#define SC_CP_REG_FIFO_COUNTL_SET_ADDR(line, cp_reg_fifo_countl,addr) \
1759
FAST_GPFLAGSET(line, cp_reg_fifo_countl,addr,CP_REG_FIFO_COUNTL_ADDR)
1760
1761
#define SC_CP_REG_FIFO_COUNTH_SET_ADDR(line, cp_reg_fifo_counth,addr) \
1762
FAST_GPFLAGSET(line, cp_reg_fifo_counth,addr,CP_REG_FIFO_COUNTH_ADDR)
1763
1764
#define SC_CP_REG_FIFO_WPTRL_SET_PAD0(line, cp_reg_fifo_wptrl,pad0) \
1765
FAST_GPFLAGSET(line, cp_reg_fifo_wptrl,pad0,CP_REG_FIFO_WPTRL_PAD0)
1766
1767
#define SC_CP_REG_FIFO_WPTRL_SET_ADDR(line, cp_reg_fifo_wptrl,addr) \
1768
FAST_GPFLAGSET(line, cp_reg_fifo_wptrl,addr,CP_REG_FIFO_WPTRL_ADDR)
1769
1770
#define SC_CP_REG_FIFO_WPTRH_SET_ADDR(line, cp_reg_fifo_wptrh,addr) \
1771
FAST_GPFLAGSET(line, cp_reg_fifo_wptrh,addr,CP_REG_FIFO_WPTRH_ADDR)
1772
1773
#define SC_CP_REG_FIFO_RPTRL_SET_PAD0(line, cp_reg_fifo_rptrl,pad0) \
1774
FAST_GPFLAGSET(line, cp_reg_fifo_rptrl,pad0,CP_REG_FIFO_RPTRL_PAD0)
1775
1776
#define SC_CP_REG_FIFO_RPTRL_SET_ADDR(line, cp_reg_fifo_rptrl,addr) \
1777
FAST_GPFLAGSET(line, cp_reg_fifo_rptrl,addr,CP_REG_FIFO_RPTRL_ADDR)
1778
1779
#define SC_CP_REG_FIFO_RPTRH_SET_ADDR(line, cp_reg_fifo_rptrh,addr) \
1780
FAST_GPFLAGSET(line, cp_reg_fifo_rptrh,addr,CP_REG_FIFO_RPTRH_ADDR)
1781
1782
#define SC_CP_REG_FIFO_BRKL_SET_PAD0(line, cp_reg_fifo_brkl,pad0) \
1783
FAST_GPFLAGSET(line, cp_reg_fifo_brkl,pad0,CP_REG_FIFO_BRKL_PAD0)
1784
1785
#define SC_CP_REG_FIFO_BRKL_SET_ADDR(line, cp_reg_fifo_brkl,addr) \
1786
FAST_GPFLAGSET(line, cp_reg_fifo_brkl,addr,CP_REG_FIFO_BRKL_ADDR)
1787
1788
#define SC_CP_REG_FIFO_BRKH_SET_ADDR(line, cp_reg_fifo_brkh,addr) \
1789
FAST_GPFLAGSET(line, cp_reg_fifo_brkh,addr,CP_REG_FIFO_BRKH_ADDR)
1790
1791
#define SC_CP_VCD_REG_LO_SET_PMIDX(line, cp_vcd_reg_lo,pmidx) \
1792
FAST_GPFLAGSET(line, cp_vcd_reg_lo,pmidx,CP_VCD_REG_LO_PMIDX)
1793
1794
#define SC_CP_VCD_REG_LO_SET_T0MIDX(line, cp_vcd_reg_lo,t0midx) \
1795
FAST_GPFLAGSET(line, cp_vcd_reg_lo,t0midx,CP_VCD_REG_LO_T0MIDX)
1796
1797
#define SC_CP_VCD_REG_LO_SET_T1MIDX(line, cp_vcd_reg_lo,t1midx) \
1798
FAST_GPFLAGSET(line, cp_vcd_reg_lo,t1midx,CP_VCD_REG_LO_T1MIDX)
1799
1800
#define SC_CP_VCD_REG_LO_SET_T2MIDX(line, cp_vcd_reg_lo,t2midx) \
1801
FAST_GPFLAGSET(line, cp_vcd_reg_lo,t2midx,CP_VCD_REG_LO_T2MIDX)
1802
1803
#define SC_CP_VCD_REG_LO_SET_T3MIDX(line, cp_vcd_reg_lo,t3midx) \
1804
FAST_GPFLAGSET(line, cp_vcd_reg_lo,t3midx,CP_VCD_REG_LO_T3MIDX)
1805
1806
#define SC_CP_VCD_REG_LO_SET_T4MIDX(line, cp_vcd_reg_lo,t4midx) \
1807
FAST_GPFLAGSET(line, cp_vcd_reg_lo,t4midx,CP_VCD_REG_LO_T4MIDX)
1808
1809
#define SC_CP_VCD_REG_LO_SET_T5MIDX(line, cp_vcd_reg_lo,t5midx) \
1810
FAST_GPFLAGSET(line, cp_vcd_reg_lo,t5midx,CP_VCD_REG_LO_T5MIDX)
1811
1812
#define SC_CP_VCD_REG_LO_SET_T6MIDX(line, cp_vcd_reg_lo,t6midx) \
1813
FAST_GPFLAGSET(line, cp_vcd_reg_lo,t6midx,CP_VCD_REG_LO_T6MIDX)
1814
1815
#define SC_CP_VCD_REG_LO_SET_T7MIDX(line, cp_vcd_reg_lo,t7midx) \
1816
FAST_GPFLAGSET(line, cp_vcd_reg_lo,t7midx,CP_VCD_REG_LO_T7MIDX)
1817
1818
#define SC_CP_VCD_REG_LO_SET_POS(line, cp_vcd_reg_lo,pos) \
1819
FAST_GPFLAGSET(line, cp_vcd_reg_lo,pos,CP_VCD_REG_LO_POS)
1820
1821
#define SC_CP_VCD_REG_LO_SET_NRM(line, cp_vcd_reg_lo,nrm) \
1822
FAST_GPFLAGSET(line, cp_vcd_reg_lo,nrm,CP_VCD_REG_LO_NRM)
1823
1824
#define SC_CP_VCD_REG_LO_SET_COL0(line, cp_vcd_reg_lo,col0) \
1825
FAST_GPFLAGSET(line, cp_vcd_reg_lo,col0,CP_VCD_REG_LO_COL0)
1826
1827
#define SC_CP_VCD_REG_LO_SET_COL1(line, cp_vcd_reg_lo,col1) \
1828
FAST_GPFLAGSET(line, cp_vcd_reg_lo,col1,CP_VCD_REG_LO_COL1)
1829
1830
#define SC_CP_VCD_REG_HI_SET_TEX0(line, cp_vcd_reg_hi,tex0) \
1831
FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex0,CP_VCD_REG_HI_TEX0)
1832
1833
#define SC_CP_VCD_REG_HI_SET_TEX1(line, cp_vcd_reg_hi,tex1) \
1834
FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex1,CP_VCD_REG_HI_TEX1)
1835
1836
#define SC_CP_VCD_REG_HI_SET_TEX2(line, cp_vcd_reg_hi,tex2) \
1837
FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex2,CP_VCD_REG_HI_TEX2)
1838
1839
#define SC_CP_VCD_REG_HI_SET_TEX3(line, cp_vcd_reg_hi,tex3) \
1840
FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex3,CP_VCD_REG_HI_TEX3)
1841
1842
#define SC_CP_VCD_REG_HI_SET_TEX4(line, cp_vcd_reg_hi,tex4) \
1843
FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex4,CP_VCD_REG_HI_TEX4)
1844
1845
#define SC_CP_VCD_REG_HI_SET_TEX5(line, cp_vcd_reg_hi,tex5) \
1846
FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex5,CP_VCD_REG_HI_TEX5)
1847
1848
#define SC_CP_VCD_REG_HI_SET_TEX6(line, cp_vcd_reg_hi,tex6) \
1849
FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex6,CP_VCD_REG_HI_TEX6)
1850
1851
#define SC_CP_VCD_REG_HI_SET_TEX7(line, cp_vcd_reg_hi,tex7) \
1852
FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex7,CP_VCD_REG_HI_TEX7)
1853
1854
#define SC_CP_VAT_REG_A_SET_POSCNT(line, cp_vat_reg_a,posCnt) \
1855
FAST_GPFLAGSET(line, cp_vat_reg_a,posCnt,CP_VAT_REG_A_POSCNT)
1856
1857
#define SC_CP_VAT_REG_A_SET_POSFMT(line, cp_vat_reg_a,posFmt) \
1858
FAST_GPFLAGSET(line, cp_vat_reg_a,posFmt,CP_VAT_REG_A_POSFMT)
1859
1860
#define SC_CP_VAT_REG_A_SET_POSSHFT(line, cp_vat_reg_a,posShft) \
1861
FAST_GPFLAGSET(line, cp_vat_reg_a,posShft,CP_VAT_REG_A_POSSHFT)
1862
1863
#define SC_CP_VAT_REG_A_SET_NRMCNT(line, cp_vat_reg_a,nrmCnt) \
1864
FAST_GPFLAGSET(line, cp_vat_reg_a,nrmCnt,CP_VAT_REG_A_NRMCNT)
1865
1866
#define SC_CP_VAT_REG_A_SET_NRMFMT(line, cp_vat_reg_a,nrmFmt) \
1867
FAST_GPFLAGSET(line, cp_vat_reg_a,nrmFmt,CP_VAT_REG_A_NRMFMT)
1868
1869
#define SC_CP_VAT_REG_A_SET_COL0CNT(line, cp_vat_reg_a,Col0Cnt) \
1870
FAST_GPFLAGSET(line, cp_vat_reg_a,Col0Cnt,CP_VAT_REG_A_COL0CNT)
1871
1872
#define SC_CP_VAT_REG_A_SET_COL0FMT(line, cp_vat_reg_a,Col0Fmt) \
1873
FAST_GPFLAGSET(line, cp_vat_reg_a,Col0Fmt,CP_VAT_REG_A_COL0FMT)
1874
1875
#define SC_CP_VAT_REG_A_SET_COL1CNT(line, cp_vat_reg_a,Col1Cnt) \
1876
FAST_GPFLAGSET(line, cp_vat_reg_a,Col1Cnt,CP_VAT_REG_A_COL1CNT)
1877
1878
#define SC_CP_VAT_REG_A_SET_COL1FMT(line, cp_vat_reg_a,Col1Fmt) \
1879
FAST_GPFLAGSET(line, cp_vat_reg_a,Col1Fmt,CP_VAT_REG_A_COL1FMT)
1880
1881
#define SC_CP_VAT_REG_A_SET_TEX0CNT(line, cp_vat_reg_a,tex0Cnt) \
1882
FAST_GPFLAGSET(line, cp_vat_reg_a,tex0Cnt,CP_VAT_REG_A_TEX0CNT)
1883
1884
#define SC_CP_VAT_REG_A_SET_TEX0FMT(line, cp_vat_reg_a,tex0Fmt) \
1885
FAST_GPFLAGSET(line, cp_vat_reg_a,tex0Fmt,CP_VAT_REG_A_TEX0FMT)
1886
1887
#define SC_CP_VAT_REG_A_SET_TEX0SHFT(line, cp_vat_reg_a,tex0Shft) \
1888
FAST_GPFLAGSET(line, cp_vat_reg_a,tex0Shft,CP_VAT_REG_A_TEX0SHFT)
1889
1890
#define SC_CP_VAT_REG_A_SET_BYTEDEQUANT(line, cp_vat_reg_a,byteDequant) \
1891
FAST_GPFLAGSET(line, cp_vat_reg_a,byteDequant,CP_VAT_REG_A_BYTEDEQUANT)
1892
1893
#define SC_CP_VAT_REG_A_SET_NORMALINDEX3(line, cp_vat_reg_a,normalIndex3) \
1894
FAST_GPFLAGSET(line, cp_vat_reg_a,normalIndex3,CP_VAT_REG_A_NORMALINDEX3)
1895
1896
#define SC_CP_VAT_REG_B_SET_TEX1CNT(line, cp_vat_reg_b,tex1Cnt) \
1897
FAST_GPFLAGSET(line, cp_vat_reg_b,tex1Cnt,CP_VAT_REG_B_TEX1CNT)
1898
1899
#define SC_CP_VAT_REG_B_SET_TEX1FMT(line, cp_vat_reg_b,tex1Fmt) \
1900
FAST_GPFLAGSET(line, cp_vat_reg_b,tex1Fmt,CP_VAT_REG_B_TEX1FMT)
1901
1902
#define SC_CP_VAT_REG_B_SET_TEX1SHFT(line, cp_vat_reg_b,tex1Shft) \
1903
FAST_GPFLAGSET(line, cp_vat_reg_b,tex1Shft,CP_VAT_REG_B_TEX1SHFT)
1904
1905
#define SC_CP_VAT_REG_B_SET_TEX2CNT(line, cp_vat_reg_b,tex2Cnt) \
1906
FAST_GPFLAGSET(line, cp_vat_reg_b,tex2Cnt,CP_VAT_REG_B_TEX2CNT)
1907
1908
#define SC_CP_VAT_REG_B_SET_TEX2FMT(line, cp_vat_reg_b,tex2Fmt) \
1909
FAST_GPFLAGSET(line, cp_vat_reg_b,tex2Fmt,CP_VAT_REG_B_TEX2FMT)
1910
1911
#define SC_CP_VAT_REG_B_SET_TEX2SHFT(line, cp_vat_reg_b,tex2Shft) \
1912
FAST_GPFLAGSET(line, cp_vat_reg_b,tex2Shft,CP_VAT_REG_B_TEX2SHFT)
1913
1914
#define SC_CP_VAT_REG_B_SET_TEX3CNT(line, cp_vat_reg_b,tex3Cnt) \
1915
FAST_GPFLAGSET(line, cp_vat_reg_b,tex3Cnt,CP_VAT_REG_B_TEX3CNT)
1916
1917
#define SC_CP_VAT_REG_B_SET_TEX3FMT(line, cp_vat_reg_b,tex3Fmt) \
1918
FAST_GPFLAGSET(line, cp_vat_reg_b,tex3Fmt,CP_VAT_REG_B_TEX3FMT)
1919
1920
#define SC_CP_VAT_REG_B_SET_TEX3SHFT(line, cp_vat_reg_b,tex3Shft) \
1921
FAST_GPFLAGSET(line, cp_vat_reg_b,tex3Shft,CP_VAT_REG_B_TEX3SHFT)
1922
1923
#define SC_CP_VAT_REG_B_SET_TEX4CNT(line, cp_vat_reg_b,tex4Cnt) \
1924
FAST_GPFLAGSET(line, cp_vat_reg_b,tex4Cnt,CP_VAT_REG_B_TEX4CNT)
1925
1926
#define SC_CP_VAT_REG_B_SET_TEX4FMT(line, cp_vat_reg_b,tex4Fmt) \
1927
FAST_GPFLAGSET(line, cp_vat_reg_b,tex4Fmt,CP_VAT_REG_B_TEX4FMT)
1928
1929
#define SC_CP_VAT_REG_B_SET_VCACHE_ENHANCE(line, cp_vat_reg_b,vcache_enhance) \
1930
FAST_GPFLAGSET(line, cp_vat_reg_b,vcache_enhance,CP_VAT_REG_B_VCACHE_ENHANCE)
1931
1932
#define SC_CP_VAT_REG_C_SET_TEX4SHFT(line, cp_vat_reg_c,tex4Shft) \
1933
FAST_GPFLAGSET(line, cp_vat_reg_c,tex4Shft,CP_VAT_REG_C_TEX4SHFT)
1934
1935
#define SC_CP_VAT_REG_C_SET_TEX5CNT(line, cp_vat_reg_c,tex5Cnt) \
1936
FAST_GPFLAGSET(line, cp_vat_reg_c,tex5Cnt,CP_VAT_REG_C_TEX5CNT)
1937
1938
#define SC_CP_VAT_REG_C_SET_TEX5FMT(line, cp_vat_reg_c,tex5Fmt) \
1939
FAST_GPFLAGSET(line, cp_vat_reg_c,tex5Fmt,CP_VAT_REG_C_TEX5FMT)
1940
1941
#define SC_CP_VAT_REG_C_SET_TEX5SHFT(line, cp_vat_reg_c,tex5Shft) \
1942
FAST_GPFLAGSET(line, cp_vat_reg_c,tex5Shft,CP_VAT_REG_C_TEX5SHFT)
1943
1944
#define SC_CP_VAT_REG_C_SET_TEX6CNT(line, cp_vat_reg_c,tex6Cnt) \
1945
FAST_GPFLAGSET(line, cp_vat_reg_c,tex6Cnt,CP_VAT_REG_C_TEX6CNT)
1946
1947
#define SC_CP_VAT_REG_C_SET_TEX6FMT(line, cp_vat_reg_c,tex6Fmt) \
1948
FAST_GPFLAGSET(line, cp_vat_reg_c,tex6Fmt,CP_VAT_REG_C_TEX6FMT)
1949
1950
#define SC_CP_VAT_REG_C_SET_TEX6SHFT(line, cp_vat_reg_c,tex6Shft) \
1951
FAST_GPFLAGSET(line, cp_vat_reg_c,tex6Shft,CP_VAT_REG_C_TEX6SHFT)
1952
1953
#define SC_CP_VAT_REG_C_SET_TEX7CNT(line, cp_vat_reg_c,tex7Cnt) \
1954
FAST_GPFLAGSET(line, cp_vat_reg_c,tex7Cnt,CP_VAT_REG_C_TEX7CNT)
1955
1956
#define SC_CP_VAT_REG_C_SET_TEX7FMT(line, cp_vat_reg_c,tex7Fmt) \
1957
FAST_GPFLAGSET(line, cp_vat_reg_c,tex7Fmt,CP_VAT_REG_C_TEX7FMT)
1958
1959
#define SC_CP_VAT_REG_C_SET_TEX7SHFT(line, cp_vat_reg_c,tex7Shft) \
1960
FAST_GPFLAGSET(line, cp_vat_reg_c,tex7Shft,CP_VAT_REG_C_TEX7SHFT)
1961
1962
#define SC_CP_MATIDX_REG_A_SET_POSIDX(line, cp_matidx_reg_a,posIdx) \
1963
FAST_GPFLAGSET(line, cp_matidx_reg_a,posIdx,CP_MATIDX_REG_A_POSIDX)
1964
1965
#define SC_CP_MATIDX_REG_A_SET_TEX0IDX(line, cp_matidx_reg_a,tex0Idx) \
1966
FAST_GPFLAGSET(line, cp_matidx_reg_a,tex0Idx,CP_MATIDX_REG_A_TEX0IDX)
1967
1968
#define SC_CP_MATIDX_REG_A_SET_TEX1IDX(line, cp_matidx_reg_a,tex1Idx) \
1969
FAST_GPFLAGSET(line, cp_matidx_reg_a,tex1Idx,CP_MATIDX_REG_A_TEX1IDX)
1970
1971
#define SC_CP_MATIDX_REG_A_SET_TEX2IDX(line, cp_matidx_reg_a,tex2Idx) \
1972
FAST_GPFLAGSET(line, cp_matidx_reg_a,tex2Idx,CP_MATIDX_REG_A_TEX2IDX)
1973
1974
#define SC_CP_MATIDX_REG_A_SET_TEX3IDX(line, cp_matidx_reg_a,tex3Idx) \
1975
FAST_GPFLAGSET(line, cp_matidx_reg_a,tex3Idx,CP_MATIDX_REG_A_TEX3IDX)
1976
1977
#define SC_CP_MATIDX_REG_B_SET_TEX4IDX(line, cp_matidx_reg_b,tex4Idx) \
1978
FAST_GPFLAGSET(line, cp_matidx_reg_b,tex4Idx,CP_MATIDX_REG_B_TEX4IDX)
1979
1980
#define SC_CP_MATIDX_REG_B_SET_TEX5IDX(line, cp_matidx_reg_b,tex5Idx) \
1981
FAST_GPFLAGSET(line, cp_matidx_reg_b,tex5Idx,CP_MATIDX_REG_B_TEX5IDX)
1982
1983
#define SC_CP_MATIDX_REG_B_SET_TEX6IDX(line, cp_matidx_reg_b,tex6Idx) \
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FAST_GPFLAGSET(line, cp_matidx_reg_b,tex6Idx,CP_MATIDX_REG_B_TEX6IDX)
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#define SC_CP_MATIDX_REG_B_SET_TEX7IDX(line, cp_matidx_reg_b,tex7Idx) \
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FAST_GPFLAGSET(line, cp_matidx_reg_b,tex7Idx,CP_MATIDX_REG_B_TEX7IDX)
1988
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#define SC_CP_ARRAY_BASE_REG_SET_BASE(line, cp_array_base_reg,base) \
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FAST_GPFLAGSET(line, cp_array_base_reg,base,CP_ARRAY_BASE_REG_BASE)
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#define SC_CP_ARRAY_BASE_REG_SET_PAD0(line, cp_array_base_reg,pad0) \
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FAST_GPFLAGSET(line, cp_array_base_reg,pad0,CP_ARRAY_BASE_REG_PAD0)
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#define SC_CP_ARRAY_STRIDE_REG_SET_STRIDE(line, cp_array_stride_reg,stride) \
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FAST_GPFLAGSET(line, cp_array_stride_reg,stride,CP_ARRAY_STRIDE_REG_STRIDE)
1997
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#define SC_CP_ARRAY_STRIDE_REG_SET_PAD0(line, cp_array_stride_reg,pad0) \
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FAST_GPFLAGSET(line, cp_array_stride_reg,pad0,CP_ARRAY_STRIDE_REG_PAD0)
2000
2001
#define SC_CP_STAT_ENABLE_REG_SET_VC_STAT(line, cp_stat_enable_reg,vc_stat) \
2002
FAST_GPFLAGSET(line, cp_stat_enable_reg,vc_stat,CP_STAT_ENABLE_REG_VC_STAT)
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#define SC_CP_STAT_ENABLE_REG_SET_PAD0(line, cp_stat_enable_reg,pad0) \
2005
FAST_GPFLAGSET(line, cp_stat_enable_reg,pad0,CP_STAT_ENABLE_REG_PAD0)
2006
2007
#define SC_CP_STAT_ENABLE_REG_SET_FRCLK(line, cp_stat_enable_reg,frclk) \
2008
FAST_GPFLAGSET(line, cp_stat_enable_reg,frclk,CP_STAT_ENABLE_REG_FRCLK)
2009
2010
#define SC_CP_STAT_SEL_REG_SET_ATTR_SEL(line, cp_stat_sel_reg,attr_sel) \
2011
FAST_GPFLAGSET(line, cp_stat_sel_reg,attr_sel,CP_STAT_SEL_REG_ATTR_SEL)
2012
2013
#define SC_CP_STAT_SEL_REG_SET_STALLPERF_SEL(line, cp_stat_sel_reg,stallperf_sel) \
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FAST_GPFLAGSET(line, cp_stat_sel_reg,stallperf_sel,CP_STAT_SEL_REG_STALLPERF_SEL)
2015
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#define SC_CP_XF_LOADREGS_SET_ADDR(line, cp_xf_loadregs,addr) \
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FAST_GPFLAGSET(line, cp_xf_loadregs,addr,CP_XF_LOADREGS_ADDR)
2018
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#define SC_CP_XF_LOADREGS_SET_CNT(line, cp_xf_loadregs,cnt) \
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FAST_GPFLAGSET(line, cp_xf_loadregs,cnt,CP_XF_LOADREGS_CNT)
2021
2022
#define SC_CP_XF_LOADINDEX_SET_ADDR(line, cp_xf_loadindex,addr) \
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FAST_GPFLAGSET(line, cp_xf_loadindex,addr,CP_XF_LOADINDEX_ADDR)
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#define SC_CP_XF_LOADINDEX_SET_CNT(line, cp_xf_loadindex,cnt) \
2026
FAST_GPFLAGSET(line, cp_xf_loadindex,cnt,CP_XF_LOADINDEX_CNT)
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#define SC_CP_XF_LOADINDEX_SET_IDX(line, cp_xf_loadindex,idx) \
2029
FAST_GPFLAGSET(line, cp_xf_loadindex,idx,CP_XF_LOADINDEX_IDX)
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#define SC_CP_CALLOBJ_D1_SET_PAD0(line, cp_callobj_d1,pad0) \
2032
FAST_GPFLAGSET(line, cp_callobj_d1,pad0,CP_CALLOBJ_D1_PAD0)
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#define SC_CP_CALLOBJ_D1_SET_ADDR(line, cp_callobj_d1,addr) \
2035
FAST_GPFLAGSET(line, cp_callobj_d1,addr,CP_CALLOBJ_D1_ADDR)
2036
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#define SC_CP_CALLOBJ_D2_SET_PAD0(line, cp_callobj_d2,pad0) \
2038
FAST_GPFLAGSET(line, cp_callobj_d2,pad0,CP_CALLOBJ_D2_PAD0)
2039
2040
#define SC_CP_CALLOBJ_D2_SET_CNT(line, cp_callobj_d2,cnt) \
2041
FAST_GPFLAGSET(line, cp_callobj_d2,cnt,CP_CALLOBJ_D2_CNT)
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#endif
/* __FDL_CP_REG_H__ */
GXFDLShortcut.h
include
revolution
private
cp_reg.h
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