Twilight Princess
Decompilation of The Legend of Zelda: Twilight Princess
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GXRegs.h
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1#ifndef GXREGS_H
2#define GXREGS_H
3
4#include <revolution/gx.h>
5
6#ifdef __cplusplus
7extern "C" {
8#endif
9
10#include <revolution/private/bp_reg.h>
11#include <revolution/private/cp_reg.h>
12#include <revolution/private/gen_reg.h>
13#include <revolution/private/pe_reg.h>
14#include <revolution/private/pi_reg.h>
15#include <revolution/private/ras_reg.h>
16#include <revolution/private/su_reg.h>
17#include <revolution/private/tev_reg.h>
18#include <revolution/private/tx_reg.h>
19#include <revolution/private/xf_mem.h>
20
21extern volatile void* __piReg;
22extern volatile void* __cpReg;
23extern volatile void* __peReg;
24extern volatile void* __memReg;
25
26#define MEM_PE_REQCOUNTH_IDX 0x27
27#define MEM_PE_REQCOUNTL_IDX 0x28
28
29/* GX fifo write helpers */
30
31#define GX_WRITE_U8(ub) \
32 GXWGFifo.u8 = (u8)(ub)
33
34#define GX_WRITE_U16(us) \
35 GXWGFifo.u16 = (u16)(us)
36
37#define GX_WRITE_U32(ui) \
38 GXWGFifo.u32 = (u32)(ui)
39
40#define GX_WRITE_F32(f) \
41 GXWGFifo.f32 = (f32)(f);
42
43
44#define GX_PI_REG_WRITE_U32(a, d) *(vu32*)((vu8*)__piReg + (a)) = (u32)(d)
45
46#define GX_PI_REG_READ_U32(a) *(vu32*)((vu8*)__piReg + (a))
47
48#define GX_CP_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__cpReg + (a)) = (u16)(d)
49
50#define GX_CP_REG_READ_U16(a) *(vu16*)((vu16*)__cpReg + (a))
51
52#define GX_CP_REG_WRITE_U32(a, d) *(vu32*)((vu16*)__cpReg + (a)) = (u32)(d)
53
54#define GX_CP_REG_READ_U32(a) *(vu32*)((vu16*)__cpReg + (a))
55
56#define GX_MEM_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__memReg + (a)) = (u16)(d)
57
58#define GX_MEM_REG_READ_U16(a) *(vu16*)((vu16*)__memReg + (a))
59
60#define GX_PE_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__peReg + (a)) = (u16)(d)
61
62#define GX_PE_REG_READ_U16(a) *(vu16*)((vu16*)__peReg + (a))
63
64#define GX_CP_IDLE_REG_READ_U16(a) GX_CP_REG_READ_U16(a)
65
66#define GX_PI_REG_WRITE_U32(a, d) *(vu32*)((vu8*)__piReg + (a)) = (u32)(d)
67
68#define GX_PI_REG_READ_U32(a) *(vu32*)((vu8*)__piReg + (a))
69
70#define GX_CP_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__cpReg + (a)) = (u16)(d)
71
72#define GX_CP_REG_READ_U16(a) *(vu16*)((vu16*)__cpReg + (a))
73
74#define GX_CP_REG_WRITE_U32(a, d) *(vu32*)((vu16*)__cpReg + (a)) = (u32)(d)
75
76#define GX_CP_REG_READ_U32(a) *(vu32*)((vu16*)__cpReg + (a))
77
78#define GX_MEM_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__memReg + (a)) = (u16)(d)
79
80#define GX_MEM_REG_READ_U16(a) *(vu16*)((vu16*)__memReg + (a))
81
82#define GX_PE_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__peReg + (a)) = (u16)(d)
83
84#define GX_PE_REG_READ_U16(a) *(vu16*)((vu16*)__peReg + (a))
85
86#define GX_CP_IDLE_REG_READ_U16(a) GX_CP_REG_READ_U16(a)
87
88#define GX_WRITE_CP_STRM_REG(addr, vtxfmt, data) \
89 { \
90 GX_WRITE_U8(CP_OPCODE(0, 1)); \
91 GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
92 GX_WRITE_U32((data)); \
93 }
94
95// needed to match some places
96#define GX_WRITE_CP_STRM_REG_alt(addr, vtxfmt, data, rAddr) \
97 { \
98 s32 regAddr; \
99 GX_WRITE_U8(CP_OPCODE(0, 1)); \
100 GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
101 GX_WRITE_U32((data)); \
102 regAddr = rAddr; \
103 }
104
105// needed to match some places
106#if DEBUG
107#define GX_WRITE_CP_STRM_REG_alt2(addr, vtxfmt, data, rAddr) \
108 { \
109 s32 regAddr; \
110 GX_WRITE_U8(CP_OPCODE(0, 1)); \
111 GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
112 GX_WRITE_U32((data)); \
113 regAddr = rAddr; \
114 if (regAddr >= 0 && regAddr < 4) { \
115 __GXData->indexBase[regAddr] = data; \
116 } \
117 }
118#else
119#define GX_WRITE_CP_STRM_REG_alt2(addr, vtxfmt, data, rAddr) GX_WRITE_CP_STRM_REG(addr, vtxfmt, data)
120#endif
121
122// needed to match some places
123#if DEBUG
124#define GX_WRITE_CP_STRM_REG_alt3(addr, vtxfmt, data, rAddr) \
125 { \
126 s32 regAddr; \
127 GX_WRITE_U8(CP_OPCODE(0, 1)); \
128 GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
129 GX_WRITE_U32((data)); \
130 regAddr = rAddr; \
131 if (regAddr >= 0 && regAddr < 4) { \
132 __GXData->indexStride[regAddr] = data; \
133 } \
134 }
135#else
136#define GX_WRITE_CP_STRM_REG_alt3(addr, vtxfmt, data, rAddr) GX_WRITE_CP_STRM_REG(addr, vtxfmt, data)
137#endif
138
139#define GX_WRITE_XF_REG(addr, data, cnt) \
140 { \
141 GX_WRITE_U8(CP_OPCODE(0, 0x2)); \
142 GX_WRITE_U32(CP_XF_LOADREGS((addr), (cnt))); \
143 GX_WRITE_U32((data)); \
144 VERIF_XF_REG(addr, data); \
145 }
146
147#define GX_WRITE_XF_MEM_U32(addr, data) GX_WRITE_U32(data)
148#define GX_WRITE_XF_MEM_F32(addr, data) GX_WRITE_F32(data)
149
150#define GX_WRITE_RA_REG(reg) \
151 { \
152 GX_WRITE_U8(CP_OPCODE(1, 0xC)); \
153 GX_WRITE_U32((reg)); \
154 VERIF_RAS_REG(reg); \
155 }
156
157#ifdef __MWERKS__
158#define GX_DEFINE_GX_READ_COUNTER(unit) \
159 inline u32 __GXRead##unit##CounterU32(u32 regAddrL, u32 regAddrH) { \
160 u32 ctrH0, ctrH1, ctrL; \
161 ctrH0 = GX_##unit##_REG_READ_U16(regAddrH); \
162 do { \
163 ctrH1 = ctrH0; \
164 ctrL = GX_##unit##_REG_READ_U16(regAddrL); \
165 ctrH0 = GX_##unit##_REG_READ_U16(regAddrH); \
166 } while (ctrH0 != ctrH1); \
167 return ((ctrH0 << 16) | ctrL); \
168 }
169#else
170#define GX_DEFINE_GX_READ_COUNTER(unit)
171#endif
172
173#ifdef __MWERKS__
174#define FAST_FLAG_SET(regOrg, newFlag, shift, size) \
175 do { \
176 (regOrg) = (u32)__rlwimi((int)(regOrg), (int)(newFlag), (shift), (32 - (shift) - (size)), (31 - (shift))); \
177 } while (0);
178#else
179#define FAST_FLAG_SET(regOrg, newFlag, shift, size)
180#endif
181
182#ifdef __cplusplus
183}
184#endif
185
186#endif // GXREGS_H
__piReg
volatile void * __piReg
Definition GXInit.c:40
__cpReg
volatile void * __cpReg
Definition GXInit.c:39
__peReg
volatile void * __peReg
Definition GXInit.c:38
__memReg
volatile void * __memReg
Definition GXInit.c:37
bp_reg.h
cp_reg.h
gen_reg.h
pe_reg.h
pi_reg.h
ras_reg.h
su_reg.h
tev_reg.h
tx_reg.h
xf_mem.h